Perlman; David J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Perlman; David J..The latest application filed is for "high reliability memory module with a fault tolerant address and command bus".

Company Profile

0.13.5

Perlman; David J. - Wappingers Falls NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High reliability memory module with a fault tolerant address and command bus Grant 8,489,936 - Gower , et al. July 16, 2	2013-07-16
High reliability memory module with a fault tolerant address and command bus Grant 7,761,771 - Gower , et al. July 20, 2	2010-07-20
High reliability memory module with a fault tolerant address and command bus Grant 7,363,533 - Gower , et al. April 22, 2	2008-04-22
High reliability memory module with a fault tolerant address and command bus App 20070250756 - Gower; Kevin C. ; et al.	2007-10-25
High Reliability Memory Module With A Fault Tolerant Address And Command Bus App 20070204200 - Gower; Kevin C. ; et al.	2007-08-30
High Reliability Memory Module With A Fault Tolerant Address And Command Bus App 20070204201 - Gower; Kevin C. ; et al.	2007-08-30
High reliability memory module with a fault tolerant address and command bus Grant 7,234,099 - Gower , et al. June 19, 2	2007-06-19
High reliability memory module with a fault tolerant address and command bus App 20060190780 - Gower; Kevin C. ; et al.	2006-08-24
High reliability memory module with a fault tolerant address and command bus App 20040205433 - Gower, Kevin C. ; et al.	2004-10-14
Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Grant 5,567,654 - Beilstein, Jr. , et al. October 22, 1	1996-10-22
Process for aligning etch masks on an integrated circuit surface using electromagnetic energy Grant 5,567,653 - Bertin , et al. October 22, 1	1996-10-22
Cube wireability enhancement with chip-to-chip alignment and thickness control Grant 5,532,519 - Bertin , et al. July 2, 1	1996-07-02
Polyimide-insulated cube package of stacked semiconductor device chips Grant 5,478,781 - Bertin , et al. December 26, 1	1995-12-26
Early row address strobe (RAS) precharge Grant 5,297,091 - Blake , et al. March 22, 1	1994-03-22
Low powder distribution inductance lead frame for semiconductor chips Grant 5,229,639 - Hansen , et al. July 20, 1	1993-07-20
Method of bonding wires to passivated chip microcircuit conductors Grant 4,341,942 - Chaudhari , et al. July 27, 1	1982-07-27
Storage Having A Plurality Of Simultaneously Accessible Locations Grant 3,643,236 - Kolankowsky , et al. February 15, 1	1972-02-15

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