Perera; Asanga H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Perera; Asanga H..The latest application filed is for "split-gate non-volatile memory (nvm) cell and method therefor".

Company Profile

0.28.13

Perera; Asanga H. - Austin TX
Perera; Asanga H. - West Lake Hills TX
Perera; Asanga H - West Lake Hills TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Split-gate non-volatile memory (NVM) cell and method therefor Grant 9,728,410 - Swift , et al. August 8, 2	2017-08-08
Method of forming different voltage devices with high-k metal gate Grant 9,368,499 - Hong , et al. June 14, 2	2016-06-14
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor Grant 9,318,568 - Perera , et al. April 19, 2	2016-04-19
Split-gate Non-volatile Memory (nvm) Cell And Method Therefor App 20160099153 - SWIFT; CRAIG T. ; et al.	2016-04-07
Integration Of A Non-volatile Memory (nvm) Cell And A Logic Transistor And Method Therefor App 20160087058 - PERERA; ASANGA H. ; et al.	2016-03-24
Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates Grant 9,275,864 - Perera , et al. March 1, 2	2016-03-01
Integrated split gate non-volatile memory cell and logic device Grant 9,252,246 - Perera , et al. February 2, 2	2016-02-02
Method of Forming Different Voltage Devices with High-K Metal Gate App 20150380408 - Hong; Cheong Min ; et al.	2015-12-31
Method of forming different voltage devices with high-K metal gate Grant 9,142,566 - Hong , et al. September 22, 2	2015-09-22
Methods and structures for charge storage isolation in split-gate memory arrays Grant 9,136,360 - Perera , et al. September 15, 2	2015-09-15
Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology Grant 9,136,129 - Perera September 15, 2	2015-09-15
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology Grant 9,129,855 - Perera , et al. September 8, 2	2015-09-08
Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor Grant 9,105,748 - Perera , et al. August 11, 2	2015-08-11
Integrated split gate non-volatile memory cell and logic structure Grant 9,082,650 - Perera , et al. July 14, 2	2015-07-14
Nonvolatile memory bitcell with inlaid high k metal select gate Grant 9,082,837 - Perera July 14, 2	2015-07-14
Non-volatile Memory (nvm) And High-k And Metal Gate Integration Using Gate-first Methodology App 20150091079 - PERERA; ASANGA H. ; et al.	2015-04-02
Non-volatile Memory (nvm) And High-k And Metal Gate Integration Using Gate-last Methodology App 20150093864 - PERERA; ASANGA H.	2015-04-02
Method of Forming Different Voltage Devices with High-K Metal Gate App 20150069524 - Hong; Cheong Min ; et al.	2015-03-12
Method of gate strapping in split-gate memory cell with inlaid gate Grant 8,969,940 - Yater , et al. March 3, 2	2015-03-03
Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates App 20150054044 - Perera; Asanga H. ; et al.	2015-02-26
Integrated Split Gate Non-volatile Memory Cell And Logic Device App 20150054050 - PERERA; ASANGA H. ; et al.	2015-02-26
Integrated Split Gate Non-volatile Memory Cell And Logic Structure App 20150054049 - PERERA; Asanga H. ; et al.	2015-02-26
Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate App 20150041875 - Perera; Asanga H.	2015-02-12
Non-volatile memory (NVM) and high-K and metal gate integration using gate-last methodology Grant 8,901,632 - Perera , et al. December 2, 2	2014-12-02
Non-volatile memory (NVM) cell, high voltage transistor, and high-K and metal gate transistor integration Grant 8,877,585 - Perera , et al. November 4, 2	2014-11-04
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology Grant 8,871,598 - Perera October 28, 2	2014-10-28
Method for forming a trench isolation structure in an integrated circuit Grant 6,524,931 - Perera February 25, 2	2003-02-25
Method for forming a semiconductor device Grant 6,362,057 - Taylor, Jr. , et al. March 26, 2	2002-03-26
Method for forming a trench isolation structure in an integrated circuit Grant 5,786,263 - Perera July 28, 1	1998-07-28
Static-random-access memory cell with trench transistor and enhanced stability Grant 5,698,893 - Perera , et al. December 16, 1	1997-12-16
Multi-step planarization process using polishing at two different pad pressures Grant 5,665,202 - Subramanian , et al. September 9, 1	1997-09-09

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