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Instruction Scheduling For A Multi-strand Out-of-order Processor
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Executing partial-width packed data instructions
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Executing partial-width packed data instructions
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Method and apparatus for floating point operations and format conversion operations
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Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system
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Shared cache structure for temporal and non-temporal instructions
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System and method for cache sharing
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Integrated co-processor configured as a PCI device
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A Method And Apparatus For Computing A Packed Sum Of Absolute Differences
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Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry
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Processing polygon meshes using mesh pool window
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Efficient utilization of write-combining buffers
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Processing Polygon Meshes Using Mesh Pool Window
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Executing partial-width packed data instructions
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Shared cache structure for temporal and non-temporal instructions
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Conversion between packed floating point data and packed 32-bit integer data in different architectural registers
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Data conversion between floating point packed format and integer scalar format
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Conversion from packed floating point data to packed 8-bit integer data in different architectural registers
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Efficient Utilization Of Write-combining Buffers
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Conversion between packed floating point data and packed 32-bit integer data in different architectural registers
Grant 6,266,769 - Abdallah , et al. July 24, 2 | 2001-07-24 |
Conversion from packed floating point data to packed 8-bit integer data in different architectural registers
Grant 6,263,426 - Abdallah , et al. July 17, 2 | 2001-07-17 |
Conversion from packed floating point data to packed 16-bit integer data in different architectural registers
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Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry
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Method and apparatus for implementing non-temporal loads
Grant 6,223,258 - Palanca , et al. April 24, 2 | 2001-04-24 |
Shared cache structure for temporal and non-temporal information using indicative bits
Grant 6,202,129 - Palanca , et al. March 13, 2 | 2001-03-13 |
Executing partial-width packed data instructions
Grant 6,192,467 - Abdallah , et al. February 20, 2 | 2001-02-20 |
Executing partial-width packed data instructions
Grant 6,122,725 - Roussel , et al. September 19, 2 | 2000-09-19 |
Method and system for optimizing write combining performance in a shared buffer structure
Grant 6,122,715 - Palanca , et al. September 19, 2 | 2000-09-19 |
Synchronization of weakly ordered write combining operations using a fencing mechanism
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