Penth; Wolfgang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Penth; Wolfgang.The latest application filed is for "reducing memory power consumption".

Company Profile

2.15.7

Penth; Wolfgang - Holzgerlingen DE
Penth; Wolfgang - Boeblingen DE
Penth; Wolfgang - Herrenberg DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 11,043,938 - Barowski , et al. June 22, 2	2021-06-22
RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption Grant 10,984,843 - Schmidt , et al. April 20, 2	2021-04-20
Reducing Memory Power Consumption App 20200279593 - Schmidt; Martin Bernhard ; et al.	2020-09-03
Digital Logic Circuit For Deterring Race Violations At An Array Test Control Boundary Using An Inverted Array Clock Signal Featu App 20200127649 - Barowski; Harry ; et al.	2020-04-23
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,587,248 - Barowski , et al.	2020-03-10
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,367,481 - Barowski , et al. July 30, 2	2019-07-30
Digital Logic Circuit App 20180212594 - Barowski; Harry ; et al.	2018-07-26
Digital Logic Circuit App 20180212595 - Barowski; Harry ; et al.	2018-07-26
Automated stressing and testing of semiconductor memory cells Grant 9,837,142 - Chan , et al. December 5, 2	2017-12-05
Automated stressing and testing of semiconductor memory cells Grant 9,805,823 - Chan , et al. October 31, 2	2017-10-31
Automatic built-in self test for memory arrays Grant 9,715,944 - Binyamini , et al. July 25, 2	2017-07-25
Stressing and testing semiconductor memory cells Grant 9,704,567 - Kugel , et al. July 11, 2	2017-07-11
Write address synchronization in 2 read/1write SRAM arrays Grant 9,437,285 - Barowski , et al. September 6, 2	2016-09-06
Write address synchronization in 2 read/1write SRAM arrays Grant 9,406,375 - Barowski , et al. August 2, 2	2016-08-02
Boost circuit for generating an adjustable boost voltage Grant 8,493,812 - Dengler , et al. July 23, 2	2013-07-23
Reduced power consumption memory circuitry Grant 8,422,313 - Buettner , et al. April 16, 2	2013-04-16
Reduced Power Consumption Memory Circuitry App 20120155188 - Buettner; Stefan ; et al.	2012-06-21
Boost Circuit For Generating An Adjustable Boost Voltage App 20120106237 - DENGLER; OSAMA ; et al.	2012-05-03
Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory Grant 7,495,949 - Buettner , et al. February 24, 2	2009-02-24
Asymmetrical Random Access Memory Cell, Memory Comprising Asymmetrical Memory Cells And Method To Operate Such A Memory App 20070189061 - Buettner; Stefan ; et al.	2007-08-16

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