loadpatents
name:-0.009166955947876
name:-0.017382144927979
name:-0.0029301643371582
Penth; Silke Patent Filings

Penth; Silke

Patent Applications and Registrations

Patent applications and USPTO patent grants for Penth; Silke.The latest application filed is for "field-effect transistor placement optimization for improved leaf cell routability".

Company Profile
2.14.9
  • Penth; Silke - Holzgerlingen DE
  • Penth; Silke - Boeblingen DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Field-effect transistor placement optimization for improved leaf cell routability
Grant 10,565,340 - Leefken , et al. Feb
2020-02-18
Field-effect transistor placement optimization for improved leaf cell routability
Grant 10,394,994 - Leefken , et al. A
2019-08-27
Field-effect Transistor Placement Optimization For Improved Leaf Cell Routability
App 20180322235 - Leefken; Iris Maria ;   et al.
2018-11-08
Field-effect Transistor Placement Optimization For Improved Leaf Cell Routability
App 20180322236 - Leefken; Iris Maria ;   et al.
2018-11-08
Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
Grant 9,997,218 - Bunce , et al. June 12, 2
2018-06-12
Layout of interconnect lines in integrated circuits
Grant 9,904,754 - Hellner , et al. February 27, 2
2018-02-27
Layout of interconnect lines in integrated circuits
Grant 9,898,571 - Hellner , et al. February 20, 2
2018-02-20
Dual Mode Operation Having Power Saving And Active Modes In A Stacked Circuit Topology With Logic Preservation
App 20180005674 - BUNCE; PAUL A. ;   et al.
2018-01-04
Managing semiconductor memory array leakage current
Grant 9,792,967 - Bunce , et al. October 17, 2
2017-10-17
Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation
Grant 9,786,339 - Bunce , et al. October 10, 2
2017-10-10
Managing semiconductor memory array leakage current
Grant 9,761,289 - Bunce , et al. September 12, 2
2017-09-12
Dual Mode Operation Having Power Saving And Active Modes In A Stacked Circuit Topology With Logic Preservation
App 20170243619 - BUNCE; PAUL A. ;   et al.
2017-08-24
Layout Of Interconnect Lines In Integrated Circuits
App 20170228487 - Hellner; Gerhard ;   et al.
2017-08-10
Layout Of Interconnect Lines In Integrated Circuits
App 20170228489 - Hellner; Gerhard ;   et al.
2017-08-10
Memory circuit
Grant 9,711,244 - Chan , et al. July 18, 2
2017-07-18
Write address synchronization in 2 read/1write SRAM arrays
Grant 9,437,285 - Barowski , et al. September 6, 2
2016-09-06
Write address synchronization in 2 read/1write SRAM arrays
Grant 9,406,375 - Barowski , et al. August 2, 2
2016-08-02
SRAM array comprising multiple cell cores
Grant 9,384,823 - Kugel , et al. July 5, 2
2016-07-05
Sram Array Comprising Multiple Cell Cores
App 20160086659 - Kugel; Michael ;   et al.
2016-03-24
Defective memory column replacement with load isolation
Grant 8,964,493 - Penth , et al. February 24, 2
2015-02-24
Local evaluation circuit for static random-access memory
Grant 8,837,235 - Chan , et al. September 16, 2
2014-09-16
Local Evaluation Circuit for Static Random-Access Memory
App 20140254290 - Chan; Yuen Hung ;   et al.
2014-09-11
Defective Memory Column Replacement With Load Isolation
App 20140192602 - Penth; Silke ;   et al.
2014-07-10

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