Peng; Neo Chee

Patent Applications and Registrations

Patent applications and USPTO patent grants for Peng; Neo Chee.The latest application filed is for "integrated circuit devices with stacked package interposers".

Company Profile

0.10.12

Peng; Neo Chee - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit devices with stacked package interposers Grant 8,058,716 - Chye , et al. November 15, 2	2011-11-15
Integrated Circuit Devices with Stacked Package Interposers App 20100065955 - Chye; Chew Beng ; et al.	2010-03-18
Integrated circuit devices with stacked package interposers Grant 7,622,798 - Chye , et al. November 24, 2	2009-11-24
Method And System For Removing Tape From Substrates App 20080308221 - Michael; Tan Kian Shing ; et al.	2008-12-18
Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths Grant 7,425,470 - Peng , et al. September 16, 2	2008-09-16
Integrated circuit devices with stacked package interposers App 20070246840 - Chye; Chew Beng ; et al.	2007-10-25
Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths Grant 7,057,281 - Peng , et al. June 6, 2	2006-06-06
Method and apparatus for cutting semiconductor wafers Grant 7,018,270 - Peng , et al. March 28, 2	2006-03-28
In-process tape bur monitoring Grant 7,004,054 - Peng February 28, 2	2006-02-28
Method and apparatus for cutting semiconductor wafers App 20050268763 - Peng, Neo Chee ; et al.	2005-12-08
Method and apparatus for cutting semiconductor wafers Grant 6,939,199 - Peng , et al. September 6, 2	2005-09-06
In-process tape bur monitoring Grant 6,845,695 - Peng January 25, 2	2005-01-25
Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths App 20050012185 - Peng, Neo Chee ; et al.	2005-01-20
Wafer dicing device and method App 20040188400 - Peng, Neo Chee ; et al.	2004-09-30
Microelectronic component assemblies employing lead frames having reduced-thickness inner lengths App 20040173899 - Peng, Neo Chee ; et al.	2004-09-09
Wafer dicing device and method Grant 6,737,606 - Peng , et al. May 18, 2	2004-05-18
In-process tape bur monitoring App 20030209117 - Peng, Neo Chee	2003-11-13
Method and apparatus for cutting semiconductor wafers App 20030203538 - Peng, Neo Chee ; et al.	2003-10-30
Method for cutting semiconductor wafers Grant 6,576,531 - Peng , et al. June 10, 2	2003-06-10
Method For Cutting Semiconductor Wafers App 20030060022 - Peng, Neo Chee ; et al.	2003-03-27
Wafer dicing device and method App 20030047543 - Peng, Neo Chee ; et al.	2003-03-13
In-process tape bur monitoring App 20020083810 - Peng, Neo Chee	2002-07-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.