loadpatents
Patent applications and USPTO patent grants for Pendurkar; Rajesh.The latest application filed is for "method and apparatus to generate system clock synchronization pulses using a pll lock detect signal".
Patent | Date |
---|---|
Method and apparatus to generate system clock synchronization pulses using a PLL lock detect signal Grant 7,696,798 - Pendurkar April 13, 2 | 2010-04-13 |
Method And Apparatus To Generate System Clock Synchronization Pulses Using A Pll Lock Detect Signal App 20090201057 - Pendurkar; Rajesh | 2009-08-13 |
MISR simulation tool for memory BIST application Grant 6,681,357 - Pendurkar January 20, 2 | 2004-01-20 |
Method for transforming stand-alone verification tests for an embedded block into serial scan test patterns for detecting manufacturing defects App 20030171906 - Parulkar, Ishwardutt ;   et al. | 2003-09-11 |
MISR simulation tool for memory BIST application App 20020184586 - Pendurkar, Rajesh | 2002-12-05 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.