Pelley, III; Perry H.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Pelley, III; Perry H..The latest application filed is for "dynamic random access memory (dram) refresh".
Company Profile
0.36.9
- Pelley, III; Perry H. - Austin TX US
- Pelley, III; Perry H. - Aloha OR
Patent Activity
| Patent | Date |
|---|---|
| Memory system with error correction and method of operation Grant 8,402,327 - Pelley, III , et al. March 19, 2 | 2013-03-19 |
| Dynamic random access memory (DRAM) refresh Grant 8,400,859 - Pelley, III , et al. March 19, 2 | 2013-03-19 |
| Testing of multiple integrated circuits Grant 8,294,483 - Pessoa , et al. October 23, 2 | 2012-10-23 |
| Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memory Grant 8,090,913 - Pelley, III , et al. January 3, 2 | 2012-01-03 |
| Dynamic Random Access Memory (dram) Refresh App 20110255357 - PELLEY, III; PERRY H. ; et al. | 2011-10-20 |
| Multiple core system Grant 8,032,030 - Pessoa , et al. October 4, 2 | 2011-10-04 |
| Dynamic random access memory (DRAM) refresh Grant 7,990,795 - Pelley, III , et al. August 2, 2 | 2011-08-02 |
| Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions Grant 7,941,637 - Pelley, III , et al. May 10, 2 | 2011-05-10 |
| Multi-core Processing System App 20110093660 - PELLEY, III; PERRY H. ; et al. | 2011-04-21 |
| Dynamic Random Access Memory (dram) Refresh App 20100208537 - Pelley, III; Perry H. ; et al. | 2010-08-19 |
| Memory System With Error Correction And Method Of Operation App 20100107037 - Pelley, III; Perry H. ; et al. | 2010-04-29 |
| Memory with level shifting word line driver and method thereof Grant 7,706,207 - Liston , et al. April 27, 2 | 2010-04-27 |
| Memory having sense time of variable duration Grant 7,668,029 - Moyer , et al. February 23, 2 | 2010-02-23 |
| Power supply selection for multiple circuits on an integrated circuit Grant 7,638,903 - Pelley, III , et al. December 29, 2 | 2009-12-29 |
| Testing Of Multiple Integrated Circuits App 20090295415 - Pessoa; Lucio F. C. ; et al. | 2009-12-03 |
| Multiple Core System App 20090297146 - Pessoa; Lucio F. C. ; et al. | 2009-12-03 |
| Multi-core Processing System App 20090259825 - Pelley, III; Perry H. ; et al. | 2009-10-15 |
| Embedded substrate interconnect for underside contact to source and drain regions Grant 7,573,101 - Pelley, III , et al. August 11, 2 | 2009-08-11 |
| Double-rate memory Grant 7,564,738 - Pelley, III , et al. July 21, 2 | 2009-07-21 |
| Memory With Level Shifting Word Line Driver And Method Thereof App 20090021990 - Liston; Thomas W. ; et al. | 2009-01-22 |
| Memory with level shifting word line driver and method thereof Grant 7,440,354 - Liston , et al. October 21, 2 | 2008-10-21 |
| Memory with clocked sense amplifier Grant 7,430,151 - Pelley, III September 30, 2 | 2008-09-30 |
| Embedded substrate interconnect for underside contact to source and drain regions Grant 7,345,344 - Pelley, III , et al. March 18, 2 | 2008-03-18 |
| Double-rate Memory App 20080037357 - Pelley, III; Perry H. ; et al. | 2008-02-14 |
| Inductive device including bond wires Grant 6,998,952 - Zhou , et al. February 14, 2 | 2006-02-14 |
| Memory device with sense amplifier and self-timed latch Grant 6,862,208 - Palmer , et al. March 1, 2 | 2005-03-01 |
| Integrated circuit with a transitor over an interconnect layer Grant 6,838,721 - Garni , et al. January 4, 2 | 2005-01-04 |
| Voltage regulator for regulating an output voltage from a charge pump and method therefor Grant 5,726,944 - Pelley, III , et al. March 10, 1 | 1998-03-10 |
| Address comparison in an inteagrated circuit memory having shared read global data lines Grant 5,572,467 - Ghassemi , et al. November 5, 1 | 1996-11-05 |
| Integrated circuit memory with column redundancy having shared read global data lines Grant 5,502,676 - Pelley, III , et al. March 26, 1 | 1996-03-26 |
| Static random access memory resistant to soft error Grant 5,303,190 - Pelley, III April 12, 1 | 1994-04-12 |
| Low di/dt BiCMOS output buffer with improved speed Grant 5,140,191 - Nogle , et al. August 18, 1 | 1992-08-18 |
| TTL to ECL input buffer Grant 4,943,743 - Pelley, III , et al. July 24, 1 | 1990-07-24 |
| Memory using distributed data line loading Grant 4,928,268 - Nogle , et al. May 22, 1 | 1990-05-22 |
| ECL to CMOS translator Grant 4,806,799 - Pelley, III , et al. February 21, 1 | 1989-02-21 |
| RAM with dual precharge circuit and write recovery circuitry Grant 4,802,129 - Hoekstra , et al. January 31, 1 | 1989-01-31 |
| Address buffer circuit for a dram Grant 4,800,531 - Dehganpour , et al. January 24, 1 | 1989-01-24 |
| Trench cell for a dram Grant 4,794,434 - Pelley, III December 27, 1 | 1988-12-27 |
| Memory with redundancy and predecoded signals Grant 4,791,615 - Pelley, III , et al. December 13, 1 | 1988-12-13 |
| Precharge of a dram data line to an intermediate voltage Grant 4,740,921 - Lewandowski , et al. April 26, 1 | 1988-04-26 |
| Technique restore for a dynamic random access memory Grant 4,710,902 - Pelley, III , et al. December 1, 1 | 1987-12-01 |
| Sense amplifier Grant 4,551,641 - Pelley, III November 5, 1 | 1985-11-05 |
| Byte-wide dynamic RAM with multiplexed internal buses Grant 4,449,207 - Kung , et al. May 15, 1 | 1984-05-15 |
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