loadpatents
name:-0.0098249912261963
name:-0.0047860145568848
name:-0.00038504600524902
Pedone; Daniel Patent Filings

Pedone; Daniel

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pedone; Daniel.The latest application filed is for "linear spacer for spacing a carrier of a package".

Company Profile
0.4.8
  • Pedone; Daniel - Muenchen DE
  • Pedone; Daniel - Munich DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Linear Spacer For Spacing A Carrier Of A Package
App 20220148934 - Fuergut; Edward ;   et al.
2022-05-12
Power semiconductor device with integrated temperature protection
Grant 11,276,680 - Pedone , et al. March 15, 2
2022-03-15
Method For Processing A Semiconductor Wafer, Semiconductor Wafer, Clip And Semiconductor Device
App 20210305198 - von Koblinski; Carsten ;   et al.
2021-09-30
Power Semiconductor Device and Method for Fabricating a Power Semiconductor Device
App 20210225795 - Otremba; Ralf ;   et al.
2021-07-22
Semiconductor Package and Method for Fabricating a Semiconductor Package
App 20210134708 - Otremba; Ralf ;   et al.
2021-05-06
Insulated gate bipolar transistor comprising negative temperature coefficient thermistor
Grant 9,825,023 - Basler , et al. November 21, 2
2017-11-21
Method for processing a semiconductor workpiece and semiconductor workpiece
Grant 9,627,335 - Henneck , et al. April 18, 2
2017-04-18
Semiconductor devices with transistor cells and thermoresistive element
Grant 9,576,944 - Laven , et al. February 21, 2
2017-02-21
Semiconductor Devices with Transistor Cells and Thermoresistive Element
App 20160163689 - Laven; Johannes Georg ;   et al.
2016-06-09
Power Semiconductor Device with Temperature Protection
App 20160133620 - Pedone; Daniel ;   et al.
2016-05-12
Insulated Gate Bipolar Transistor Comprising Negative Temperature Coefficient Thermistor
App 20160111415 - Basler; Thomas ;   et al.
2016-04-21
Method for Processing a Semiconductor Workpiece and Semiconductor Workpiece
App 20150325535 - HENNECK; Stephan ;   et al.
2015-11-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed