Pechanek; Gerald George

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pechanek; Gerald George.The latest application filed is for "methods and apparatus for sharing nodes in a network with connections based on 1 to k+1 adjacency used in an execution array mem".

Company Profile

4.107.56

Pechanek; Gerald George - Cary NC
Pechanek; Gerald George - Endwell NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for sharing nodes in a network with connections based on 1 to k+1 adjacency used in an execution array memory array (XarMa) processor Grant 11,249,939 - Pechanek February 15, 2	2022-02-15
Methods and Apparatus for Sharing Nodes in a Network with Connections Based on 1 to K+1 Adjacency Used in an Execution Array Mem App 20200250131 - Kind Code	2020-08-06
Methods and apparatus for adjacency network delivery of operands to instruction specified destinations that reduces storage of temporary variables Grant 10,503,515 - Pechanek Dec	2019-12-10
Methods and apparatus for signal flow graph pipelining in an array processing unit that reduces storage of temporary variables Grant 10,078,517 - Pechanek September 18, 2	2018-09-18
Methods And Apparatus For Adjacency Network Delivery Of Operands To Instruction Specified Destinations That Reduces Storage Of Temporary Variables App 20180189068 - Pechanek; Gerald George	2018-07-05
Methods and apparatus for transforming, loading, and executing super-set instructions Grant 9,672,033 - Pechanek , et al. June 6, 2	2017-06-06
Methods And Apparatus For Signal Flow Graph Pipelining In An Array Processing Unit That Reduces Storage Of Temporary Variables App 20160357569 - Pechanek; Gerald George	2016-12-08
Methods and apparatus for signal flow graph pipelining that reduce storage of temporary variables Grant 9,507,603 - Pechanek November 29, 2	2016-11-29
Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructions Grant 9,460,048 - Pechanek October 4, 2	2016-10-04
Communicaton across shared mutually exclusive direction paths between clustered processing elements Grant 9,390,057 - Pechanek , et al. July 12, 2	2016-07-12
Methods and apparatus for adapting pipeline stage latency based on instruction type Grant 9,329,866 - Barry , et al. May 3, 2	2016-05-03
Methods and apparatus for motion search refinement in a SIMD array processor Grant 9,300,958 - Stojancic , et al. March 29, 2	2016-03-29
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation Grant 9,075,651 - Pechanek , et al. July 7, 2	2015-07-07
Methods and apparatus for independent processor node operations in a SIMD array processor Grant 9,063,722 - Pechanek , et al. June 23, 2	2015-06-23
Methods and apparatus for providing a scalable deblocking filtering assist function within an array processor Grant 9,060,169 - Stojancic , et al. June 16, 2	2015-06-16
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Grant 9,015,354 - Pitsianis , et al. April 21, 2	2015-04-21
System core for transferring data between an external device and memory Grant 9,009,365 - Pechanek , et al. April 14, 2	2015-04-14
Efficient Complex Multiplication and Fast Fourier Transform (FFT) Implementation on the ManArray Architecture App 20150039856 - Pitsianis; Nikos P. ; et al.	2015-02-05
Methods And Apparatus For Signal Flow Graph Pipelining That Reduce Storage Of Temporary Variables App 20150039855 - Pechanek; Gerald George	2015-02-05
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Grant 8,904,152 - Pitsianis , et al. December 2, 2	2014-12-02
Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor App 20140314152 - Stojancic; Mihailo M. ; et al.	2014-10-23
Methods and apparatus for scalable array processor interrupt detection and response Grant 8,751,772 - Barry , et al. June 10, 2	2014-06-10
Methods and apparatus for address translation functions Grant 8,713,284 - Barry , et al. April 29, 2	2014-04-29
Methods and apparatus for motion search refinement in a SIMD array processor Grant 8,693,548 - Stojancic , et al. April 8, 2	2014-04-08
Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type App 20140075157 - Barry; Edwin Franklin ; et al.	2014-03-13
Staging register file for use with multi-stage execution units Grant 8,671,266 - Pechanek , et al. March 11, 2	2014-03-11
System Core for Transferring Data Between an External Device and Memory App 20140059324 - Pechanek; Gerald George ; et al.	2014-02-27
Methods And Apparatus For Providing A Scalable Deblocking Filtering Assist Function Within An Array Processor App 20130343466 - Stojancic; Mihailo M. ; et al.	2013-12-26
Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response App 20130283012 - Barry; Edwin Franklin ; et al.	2013-10-24
Methods and Apparatus For Attaching Application Specific Functions Within An Array Processor App 20130283007 - Pechanek; Gerald George ; et al.	2013-10-24
Methods and apparatus for providing a scalable deblocking filtering assist function within an array processor Grant 8,542,744 - Stojancic , et al. September 24, 2	2013-09-24
Interconnection Network Connecting Operation-configurable Nodes According To One Or More Levels Of Adjacency In Multiple Dimensions Of Communication In A Multi-processor And A Neural Processor App 20130198488 - Pechanek; Gerald George	2013-08-01
Methods And Apparatus For Motion Search Refinement In A SIMD Array Processor App 20130182771 - Stojancic; Mihailo M. ; et al.	2013-07-18
Methods and apparatus for scalable array processor interrupt detection and response Grant 8,489,858 - Barry , et al. July 16, 2	2013-07-16
Methods and apparatus for attaching application specific functions within an array processor Grant 8,484,444 - Pechanek , et al. July 9, 2	2013-07-09
Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor Grant 8,443,169 - Pechanek May 14, 2	2013-05-14
Methods and apparatus for adapting pipeline stage latency based on instruction type Grant 8,413,086 - Barry , et al. April 2, 2	2013-04-02
System core for transferring data between an external device and memory Grant 8,397,000 - Pechanek , et al. March 12, 2	2013-03-12
Methods and apparatus for motion search refinement in a SIMD array processor Grant 8,385,419 - Stojancic , et al. February 26, 2	2013-02-26
Methods and apparatus for providing a scalable motion estimation/compensation assist function within an array processor Grant 8,358,695 - Stojancic , et al. January 22, 2	2013-01-22
Twisted and wrapped array organized into clusters of processing elements Grant 8,341,381 - Pechanek , et al. December 25, 2	2012-12-25
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation Grant 8,335,812 - Pechanek , et al. December 18, 2	2012-12-18
System core for transferring data between an external device and memory Grant 8,296,479 - Pechanek , et al. October 23, 2	2012-10-23
Meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors Grant 8,266,410 - Pechanek September 11, 2	2012-09-11
Methods and apparatus for address translation functions Grant 8,255,664 - Barry , et al. August 28, 2	2012-08-28
Methods and apparatus for quarter-pel refinement in a SIMD array processor Grant 8,208,553 - Stojancic , et al. June 26, 2	2012-06-26
Methods and apparatus for single stage Galois field operations Grant 8,195,732 - Pitsianis , et al. June 5, 2	2012-06-05
Methods And Apparatus For Independent Processor Node Operations In A SIMD Array Processor App 20120131310 - Pechanek; Gerald George ; et al.	2012-05-24
Methods and apparatus for scalable array processor interrupt detection and response Grant 8,161,267 - Barry , et al. April 17, 2	2012-04-17
Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimension Grant 8,156,311 - Pechanek April 10, 2	2012-04-10
System core for transferring data between an external device and memory Grant 8,117,357 - Pechanek , et al. February 14, 2	2012-02-14
Methods and apparatus for independent processor node operations in a SIMD array processor Grant 8,103,854 - Pechanek , et al. January 24, 2	2012-01-24
Methods and apparatus for dynamic instruction controlled reconfigurable register file Grant 8,069,337 - Pechanek , et al. November 29, 2	2011-11-29
Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution App 20110225396 - Pechanek; Gerald George ; et al.	2011-09-15
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File App 20110213952 - Pechanek; Gerald George ; et al.	2011-09-01
Methods and Apparatus for Address Translation Functions App 20110213937 - Barry; Edwin Franklin ; et al.	2011-09-01
Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor App 20110161625 - Pechanek; Gerald George	2011-06-30
Methods and apparatus for attaching application specific functions within an array processor Grant 7,971,036 - Pechanek , et al. June 28, 2	2011-06-28
Methods and Apparatus for Attaching Application Specific Functions Within an Array Processor App 20110153998 - Pechanek; Gerald George ; et al.	2011-06-23
Methods and apparatus storing expanded width instructions in a VLIW memory deferred execution Grant 7,962,723 - Pechanek , et al. June 14, 2	2011-06-14
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Grant 7,962,719 - Pitsianis , et al. June 14, 2	2011-06-14
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture Grant 7,953,955 - Larin , et al. May 31, 2	2011-05-31
Methods and apparatus for address translation functions Grant 7,945,760 - Barry , et al. May 17, 2	2011-05-17
Methods and apparatus for dynamic instruction controlled reconfigurable register file Grant 7,941,648 - Pechanek , et al. May 10, 2	2011-05-10
Methods And Apparatus For Automated Generation Of Abbreviated Instruction Set And Configurable Processor Architecture App 20110083001 - Larin; Sergei Yurievich ; et al.	2011-04-07
Methods and apparatus for efficiently sharing memory and processing in a multi-processor App 20110072237 - Pechanek; Gerald George	2011-03-24
Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimension Grant 7,886,128 - Pechanek February 8, 2	2011-02-08
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture Grant 7,865,692 - Larin , et al. January 4, 2	2011-01-04
Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type App 20100318775 - Barry; Edwin Franklin ; et al.	2010-12-16
Methods and apparatus for scalable array processor interrupt detection and response Grant 7,853,779 - Barry , et al. December 14, 2	2010-12-14
Methods and apparatus for power control in a scalable array of processor elements Grant 7,836,317 - Marchand , et al. November 16, 2	2010-11-16
Methods and apparatus for adapting pipeline stage latency based on instruction type Grant 7,809,932 - Barry , et al. October 5, 2	2010-10-05
Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication Grant RE41,703 - Pechanek , et al. September 14, 2	2010-09-14
Methods and apparatus for independent processor node operations in a SIMD array processor Grant 7,730,280 - Pechanek , et al. June 1, 2	2010-06-01
Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target register Grant 7,685,408 - Wolff , et al. March 23, 2	2010-03-23
Methods and apparatus for efficient complex long multiplication and covariance matrix implementation Grant 7,680,873 - Pechanek , et al. March 16, 2	2010-03-16
Processor organized in clusters of processing elements and cluster interconnections by a clustering process Grant 7,631,165 - Pechanek , et al. December 8, 2	2009-12-08
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor Grant RE41,012 - Barry , et al. November 24, 2	2009-11-24
Methods and Apparatus storing expanded width instructions in a VLIW memory for deferred execution App 20090276576 - Pechanek; Gerald George ; et al.	2009-11-05
Methods and Apparatus for Efficiently Sharing Memory and Processing in a Multi-Processor App 20090265512 - Pechanek; Gerald George	2009-10-22
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions Grant 7,581,079 - Pechanek August 25, 2	2009-08-25
Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision Grant RE40,883 - Pechanek , et al. August 25, 2	2009-08-25
Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution Grant 7,577,824 - Pechanek , et al. August 18, 2	2009-08-18
Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors App 20090144502 - Pechanek; Gerald George	2009-06-04
Methods and Apparatus for Transforming, Loading, and Executing Super-Set Instructions App 20090119489 - Pechanek; Gerald George ; et al.	2009-05-07
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors Grant 7,509,483 - Pechanek March 24, 2	2009-03-24
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions Grant 7,506,137 - Pechanek , et al. March 17, 2	2009-03-17
Methods and Apparatus for Single Stage Galois Field Operations App 20090063606 - Pitsianis; Nikos P. ; et al.	2009-03-05
Methods and apparatus for transforming, loading, and executing super-set instructions Grant 7,493,474 - Pechanek , et al. February 17, 2	2009-02-17
Methods and Apparatus for a Bit Rake Instruction App 20090019269 - Wolff; Edward A. ; et al.	2009-01-15
Methods and apparatus for single stage Galois field operations Grant 7,464,128 - Pitsianis , et al. December 9, 2	2008-12-09
Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File App 20080235496 - Pechanek; Gerald George ; et al.	2008-09-25
Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture Grant RE40,509 - Pechanek , et al. September 16, 2	2008-09-16
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Grant 7,424,594 - Pitsianis , et al. September 9, 2	2008-09-09
Methods and apparatus for dynamic instruction controlled reconfigurable register file Grant 7,398,347 - Pechanek , et al. July 8, 2	2008-07-08
Methods and apparatus for scalable array processor interrupt detection and response Grant 7,386,710 - Barry , et al. June 10, 2	2008-06-10
Methods and Apparatus For Providing A Scalable Motion Estimation/Compensation Assist Function Within An Array Processor App 20080059546 - Stojancic; Mihailo M. ; et al.	2008-03-06
Providing parallel operand functions using register file and extra path storage Grant 7,340,591 - Pechanek , et al. March 4, 2	2008-03-04
Methods and Apparatus For Independent Processor Node Operations In A SIMD Array Processor App 20080046685 - Pechanek; Gerald George ; et al.	2008-02-21
Methods and Apparatus For Providing A Scalable Deblocking Filtering Assist Function Within An Array Processor App 20080037650 - Stojancic; Mihailo M. ; et al.	2008-02-14
Methods and Apparatus For Quarter-Pel Refinement In A SIMD Array Processor App 20080037647 - Stojancic; Mihailo M. ; et al.	2008-02-14
Methods and Apparatus For Motion Search Refinement In A SIMD Array Processor App 20080040411 - Stojancic; Mihailo M. ; et al.	2008-02-14
Methods and Apparatus For Attaching Application Specific Functions Within An Array Processor App 20080040585 - Pechanek; Gerald George ; et al.	2008-02-14
Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques Grant 7,272,700 - Pechanek , et al. September 18, 2	2007-09-18
System core for transferring data between an external device and memory Grant 7,266,620 - Pechanek , et al. September 4, 2	2007-09-04
Methods and apparatus for power control in a scalable array of processor elements Grant 7,263,624 - Marchand , et al. August 28, 2	2007-08-28
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions Grant 7,257,696 - Pechanek , et al. August 14, 2	2007-08-14
Methods and Apparatus for Meta-Architecture Defined Programmable Instruction Fetch Functions Supporting Assembled Variable Length Instruction Processors App 20070180440 - Pechanek; Gerald George	2007-08-02
Methods and apparatus for providing context switching between software tasks with reconfigurable control Grant 7,237,088 - Barry , et al. June 26, 2	2007-06-26
Manifold array processor Grant 7,197,624 - Pechanek , et al. March 27, 2	2007-03-27
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors Grant 7,185,177 - Pechanek February 27, 2	2007-02-27
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution Grant 7,146,487 - Drabenstott , et al. December 5, 2	2006-12-05
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture App 20060150170 - Larin; Sergei Yurievich ; et al.	2006-07-06
Cascaded event detection modules for generating combined events interrupt for processor action Grant 7,058,790 - Barry , et al. June 6, 2	2006-06-06
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture Grant 7,028,286 - Larin , et al. April 11, 2	2006-04-11
Methods and apparatus for general deferred execution processors App 20050055539 - Pechanek, Gerald George ; et al.	2005-03-10
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions App 20040054871 - Pechanek, Gerald George ; et al.	2004-03-18
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors App 20040039896 - Pechanek, Gerald George	2004-02-26
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture App 20040015931 - Larin, Sergei Yurievich ; et al.	2004-01-22
Methods and apparatus for a bit rake instruction App 20030105945 - Wolff, Edward A. ; et al.	2003-06-05
Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution App 20020178345 - Drabenstott, Thomas L. ; et al.	2002-11-28
Methods and apparatus for ManArray PE-PE switch control App 20020144082 - Barry, Edwin Franklin ; et al.	2002-10-03
Massively parallel array processor Grant 6,405,185 - Pechanek , et al. June 11, 2	2002-06-11
Massively parallel multiple-folded clustered processor mesh array Grant 6,041,398 - Pechanek , et al. March 21, 2	2000-03-21
Massively parallel diagonal-fold tree array processor Grant 5,682,544 - Pechanek , et al. October 28, 1	1997-10-28
Scalable parallel group partitioned diagonal-fold switching tree computing apparatus Grant 5,640,586 - Pechanek , et al. June 17, 1	1997-06-17