| Patent | Date |
|---|
Methods for performing a non-contact electrical measurement on a cell, chip, wafer, die, or logic block
Grant 11,340,293 - De , et al. May 24, 2 | 2022-05-24 |
Methods for aligning a particle beam and performing a non-contact electrical measurement on a cell using a registration cell
Grant 11,328,899 - De , et al. May 10, 2 | 2022-05-10 |
Predicting die susceptible to early lifetime failure
Grant 11,328,108 - Burch , et al. May 10, 2 | 2022-05-10 |
Maintenance scheduling for semiconductor manufacturing equipment
Grant 11,295,993 - Honda , et al. April 5, 2 | 2022-04-05 |
Sequenced Approach For Determining Wafer Path Quality
App 20220066410 - Honda; Tomonori ; et al. | 2022-03-03 |
Pattern-Enhanced Spatial Correlation of Test Structures to Die Level Responses
App 20220043436 - Burch; Richard ; et al. | 2022-02-10 |
Automatic Window Generation for Process Trace
App 20220027248 - Burch; Richard ; et al. | 2022-01-27 |
Predicting Equipment Fail Mode from Process Trace
App 20220027230 - Burch; Richard ; et al. | 2022-01-27 |
Wafer Bin Map Based Root Cause Analysis
App 20210342993 - Honda; Tomonori ; et al. | 2021-11-04 |
Abnormal Wafer Image Classification
App 20210334608 - Honda; Tomonori ; et al. | 2021-10-28 |
Rational Decision-Making Tool for Semiconductor Processes
App 20210294950 - Honda; Tomonori ; et al. | 2021-09-23 |
Predicting Die Susceptible to Early Lifetime Failure
App 20210279388 - Burch; Richard ; et al. | 2021-09-09 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,107,804 - Lam , et al. August 31, 2 | 2021-08-31 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,081,477 - Lam , et al. August 3, 2 | 2021-08-03 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,081,476 - Lam , et al. August 3, 2 | 2021-08-03 |
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Grant 11,075,194 - Lam , et al. July 27, 2 | 2021-07-27 |
Generating robust machine learning predictions for semiconductor manufacturing processes
Grant 11,029,673 - Honda , et al. June 8, 2 | 2021-06-08 |
Failure detection and classsification using sensor data and/or measurement data
Grant 11,029,359 - Honda , et al. June 8, 2 | 2021-06-08 |
Semiconductor yield prediction
Grant 11,022,642 - David , et al. June 1, 2 | 2021-06-01 |
IC with test structures and e-beam pads embedded within a contiguous standard cell area
Grant 11,018,126 - Lam , et al. May 25, 2 | 2021-05-25 |
Collaborative Learning Model for Semiconductor Applications
App 20210142122 - Honda; Tomonori ; et al. | 2021-05-13 |
Die Level Product Modeling Without Die Level Input Data
App 20210118754 - Burch; Richard ; et al. | 2021-04-22 |
Machine Learning Variable Selection And Root Cause Discovery By Cumulative Prediction
App 20210117861 - Burch; Richard ; et al. | 2021-04-22 |
IC with test structures and E-beam pads embedded within a contiguous standard cell area
Grant 10,978,438 - Lam , et al. April 13, 2 | 2021-04-13 |
Anomalous Equipment Trace Detection and Classification
App 20210103489 - Burch; Richard ; et al. | 2021-04-08 |
Systems, Devices, And Methods For Aligning A Particle Beam And Performing A Non-contact Electrical Measurement On A Cell And/or Non-contact Electrical Measurement Cell Vehicle Using A Registration Cell
App 20210098229 - DE; Indranil ; et al. | 2021-04-01 |
Systems, Devices, And Methods For Performing A Non-contact Electrical Measurement On A Cell, Non-contact Electrical Measurement Cell Vehicle, Chip, Wafer, Die, Or Logic Block
App 20210096179 - DE; Indranil ; et al. | 2021-04-01 |
Characterization vehicles for printed circuit board and system design
Grant 10,897,814 - Stine January 19, 2 | 2021-01-19 |
Maintenance Scheduling For Semiconductor Manufacturing Equipment
App 20200388545 - Honda; Tomonori ; et al. | 2020-12-10 |
Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies
Grant 10,852,337 - Saxena , et al. December 1, 2 | 2020-12-01 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with res
Grant 10,854,522 - Lam , et al. December 1, 2 | 2020-12-01 |
Snap-to valid pattern system and method
Grant 10,803,221 - Lagnese , et al. October 13, 2 | 2020-10-13 |
IC with test structures embedded within a contiguous standard cell area
Grant 10,777,472 - Lam , et al. Sept | 2020-09-15 |
Selective inclusion/exclusion of semiconductor chips in accelerated failure tests
Grant 10,777,470 - Cheong , et al. Sept | 2020-09-15 |
Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure
Grant 10,768,222 - Brozek Sep | 2020-09-08 |
Process control techniques for semiconductor manufacturing processes
Grant 10,734,293 - David | 2020-08-04 |
Direct memory characterization using periphery transistors
Grant 10,679,723 - Lee , et al. | 2020-06-09 |
Failure detection for wire bonding in semiconductors
Grant 10,656,204 - Stine , et al. | 2020-05-19 |
Passive array test structure for cross-point memory characterization
Grant 10,643,735 - Brozek , et al. | 2020-05-05 |
Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors
Grant 10,641,804 - Saxena | 2020-05-05 |
Characterization Vehicles For Printed Circuit Board And System Design
App 20200120791 - Stine; Brian E. | 2020-04-16 |
IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same
Grant 10,622,344 - Haigh , et al. | 2020-04-14 |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells
Grant 10,593,604 - Lam , et al. | 2020-03-17 |
Standard cell design conformance using boolean assertions
Grant 10,565,344 - Lagnese Feb | 2020-02-18 |
Method for manufacturing a semiconductor product wafer
Grant 10,546,792 - Doong , et al. Ja | 2020-01-28 |
Test structures and method for electrical measurement of FinFET fin height
Grant 10,529,631 - Saxena , et al. J | 2020-01-07 |
Characterization vehicles for printed circuit board and system design
Grant 10,517,169 - Stine Dec | 2019-12-24 |
Characterization Vehicles For Printed Circuit Board And System Design
App 20190320525 - Stine; Brian E. | 2019-10-17 |
Direct access memory characterization vehicle
Grant 10,410,735 - Doong , et al. Sept | 2019-09-10 |
Direct probing characterization vehicle for transistor, capacitor and resistor testing
Grant 10,380,305 - Doong , et al. A | 2019-08-13 |
Failure Detection For Wire Bonding In Semiconductors
App 20190146032 - Stine; Brian ; et al. | 2019-05-16 |
Methods for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective tip-to-t
Grant 10,290,552 - Lam , et al. | 2019-05-14 |
Advanced manufacturing insight system for semiconductor application
Grant 10,268,562 - Stine , et al. | 2019-04-23 |
Integrated circuit containing first and second DOEs of standard Cell Compatible, NCEM-enabled Fill Cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including corner short configured fill cells
Grant 10,269,786 - Lam , et al. | 2019-04-23 |
Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
Grant 10,263,011 - Haigh | 2019-04-16 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated wit
Grant 10,211,111 - Lam , et al. Feb | 2019-02-19 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from non-contact pads associat
Grant 10,211,112 - Lam , et al. Feb | 2019-02-19 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of a least one side-to-side short or leakage, at least one via-chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from cells with respective side-to-
Grant 10,199,294 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for m
Grant 10,199,283 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas
Grant 10,199,285 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor water using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated w
Grant 10,199,293 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with re
Grant 10,199,287 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one chamfer short or leakage, and at least one corner short or leakage, where such measurements are obtained from non-contact pads associated with r
Grant 10,199,286 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one side-to-side short or leakage, where such measurements are obtained from cells with respective tip
Grant 10,199,290 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one chamfer short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respect
Grant 10,199,289 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with re
Grant 10,199,288 - Lam , et al. Fe | 2019-02-05 |
Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one tip-to-side short or leakage, and at least one chamfer short or leakage, where such measurements are obtained from non-contact pads associated wi
Grant 10,199,284 - Lam , et al. Fe | 2019-02-05 |
Integrated circuit including NCEM-enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 10,109,539 - Lam , et al. October 23, 2 | 2018-10-23 |
Method for automatically determining proposed standard cell design conformance based upon template constraints
Grant 10,102,330 - Lagnese , et al. October 16, 2 | 2018-10-16 |
On-chip capacitance measurement for memory characterization vehicle
Grant 10,096,378 - Doong , et al. October 9, 2 | 2018-10-09 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 10,096,529 - Lam , et al. October 9, 2 | 2018-10-09 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 10,096,530 - Lam , et al. October 9, 2 | 2018-10-09 |
Integrated circuit containing DOEs of GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells
Grant 9,984,944 - Lam , et al. May 29, 2 | 2018-05-29 |
Advanced node standard logic cells that utilizes TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs
Grant 9,984,970 - Haigh May 29, 2 | 2018-05-29 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of GATECNT-GATE via opens
Grant 9,953,889 - Lam , et al. April 24, 2 | 2018-04-24 |
Method for accurate measurement of leaky capacitors using charge based capacitance measurements
Grant 9,952,268 - Saxena , et al. April 24, 2 | 2018-04-24 |
Method For Manufacturing A Semiconductor Product Wafer
App 20180108580 - DOONG; Yih-Yuh Kelvin ; et al. | 2018-04-19 |
Integrated circuit including NCEM-enabled, side-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,947,601 - Lam , et al. April 17, 2 | 2018-04-17 |
Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,929,063 - Lam , et al. March 27, 2 | 2018-03-27 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-Enabled fill cells, with the first DOE including tip-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,929,136 - Lam , et al. March 27, 2 | 2018-03-27 |
Integrated circuit including NCEM-enabled, snake-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,922,890 - Lam , et al. March 20, 2 | 2018-03-20 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,922,968 - Lam , et al. March 20, 2 | 2018-03-20 |
Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,911,668 - Lam , et al. March 6, 2 | 2018-03-06 |
Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gate
Grant 9,911,670 - Lam , et al. March 6, 2 | 2018-03-06 |
Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,911,669 - Lam , et al. March 6, 2 | 2018-03-06 |
Process for making and using mesh-style NCEM pads
Grant 9,911,649 - Lam , et al. March 6, 2 | 2018-03-06 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
Grant 9,905,553 - Lam , et al. February 27, 2 | 2018-02-27 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of V0 via opens
Grant 9,905,487 - Lam , et al. February 27, 2 | 2018-02-27 |
Process for making an integrated circuit that includes NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,899,276 - Lam , et al. February 20, 2 | 2018-02-20 |
Integrated circuit including NCEM-Enabled, tip-to-tip gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,881,843 - Lam , et al. January 30, 2 | 2018-01-30 |
Snap-to valid pattern system and method
Grant 9,870,441 - Lagnese , et al. January 16, 2 | 2018-01-16 |
Integrated circuit including NCEM-enabled, interlayer overlap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
Grant 9,870,962 - Lam , et al. January 16, 2 | 2018-01-16 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,871,028 - Lam , et al. January 16, 2 | 2018-01-16 |
Process for making semiconductor dies, chips and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on test wafers that include multiple means/steps for enabling NC detection of AACNT-TS via opens
Grant 9,870,966 - Lam , et al. January 16, 2 | 2018-01-16 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 9,865,583 - Lam , et al. January 9, 2 | 2018-01-09 |
Method for manufacturing a semiconductor product wafer
Grant 9,847,264 - Doong , et al. December 19, 2 | 2017-12-19 |
Integrated circuit containing DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Grant 9,831,141 - Lam , et al. November 28, 2 | 2017-11-28 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,825,018 - Lam , et al. November 21, 2 | 2017-11-21 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells with first DOE including tip-to-side short configured fill cells and second DOE including chamfer short configured fill cells
Grant 9,818,738 - Lam , et al. November 14, 2 | 2017-11-14 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,818,660 - Lam , et al. November 14, 2 | 2017-11-14 |
Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads
Grant 9,805,994 - Lam , et al. October 31, 2 | 2017-10-31 |
Test Structures For Measuring Silicon Thickness In Fully Depleted Silicon-on-insulator Technologies
App 20170309524 - Saxena; Sharad ; et al. | 2017-10-26 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
Grant 9,799,640 - Lam , et al. October 24, 2 | 2017-10-24 |
Integrated circuit containing DOEs of NCEM-enabled fill cells
Grant 9,799,575 - Lam , et al. October 24, 2 | 2017-10-24 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least Via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured NCEM-enabled fill cells
Grant 9,793,253 - Lam , et al. October 17, 2 | 2017-10-17 |
E-beam inspection apparatus and method of using the same on various integrated circuit chips
Grant 9,793,090 - De , et al. October 17, 2 | 2017-10-17 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,786,648 - Lam , et al. October 10, 2 | 2017-10-10 |
Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens
Grant 9,785,496 - Lam , et al. October 10, 2 | 2017-10-10 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
Grant 9,786,649 - Lam , et al. October 10, 2 | 2017-10-10 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,786,650 - Lam , et al. October 10, 2 | 2017-10-10 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, TS-short-configured, metal-short configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,780,083 - Lam , et al. October 3, 2 | 2017-10-03 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,778,974 - Lam , et al. October 3, 2 | 2017-10-03 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
Grant 9,773,774 - Lam , et al. September 26, 2 | 2017-09-26 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enabled fill cells
Grant 9,773,773 - Lam , et al. September 26, 2 | 2017-09-26 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
Grant 9,773,775 - Lam , et al. September 26, 2 | 2017-09-26 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including metal island open configured fill cells
Grant 9,766,970 - Lam , et al. September 19, 2 | 2017-09-19 |
Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
Grant 9,768,083 - Lam , et al. September 19, 2 | 2017-09-19 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including chamfer short configured fill cells
Grant 9,768,156 - Lam , et al. September 19, 2 | 2017-09-19 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,761,573 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATECNT-short-configured, metal-short-configured, and AA-short-configured, NCEM-enabled fill cells
Grant 9,761,574 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least chamfer-short-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells
Grant 9,761,575 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including merged-via configured fill cells
Grant 9,761,502 - Lam , et al. September 12, 2 | 2017-09-12 |
Integrated Circuit Containing DOEs of NCEM-enabled Fill Cells
App 20170178981 - Lam; Stephen ; et al. | 2017-06-22 |
E-beam Inspection Apparatus And Method Of Using The Same On Various Integrated Circuit Chips
App 20160118217 - De; Indranil ; et al. | 2016-04-28 |
Opportunistic Placement Of Ic Test Strucutres And/or E-beam Target Pads In Areas Otherwise Used For Filler Cells, Tap Cells, Decap Cells, Scribe Lines, And/or Dummy Fill, As Well As Product Ic Chips Containing Same
App 20150270181 - De; Indranil ; et al. | 2015-09-24 |
Layout For Dut Arrays Used In Semiconductor Wafer Testing
App 20090140762 - Hess; Christopher ; et al. | 2009-06-04 |
System And Method For Product Yield Prediction
App 20080282210 - Stine; Brian E. ; et al. | 2008-11-13 |
Test Cells for semiconductor yield improvement
App 20080169466 - Stine; Brian ; et al. | 2008-07-17 |
Method For Electron Beam Proximity Effect Correction
App 20080067446 - Belic; Nikola ; et al. | 2008-03-20 |
Layout compiler
App 20070268731 - Weiland; Larg H. ; et al. | 2007-11-22 |
System and method for product yield prediction
App 20070118242 - Stine; Brian E. ; et al. | 2007-05-24 |
Adjusting die placement on a semiconductor wafer to increase yield
App 20070105273 - Cadouri; Eitan | 2007-05-10 |
Layout for DUT arrays used in semiconductor wafer testing
App 20070075718 - Hess; Christopher ; et al. | 2007-04-05 |
Semiconductor wafer with non-rectangular shaped dice
App 20060278956 - Cadouri; Eitan | 2006-12-14 |
System and method for product yield prediction
App 20060277506 - Stine; Brian E. ; et al. | 2006-12-07 |
Yield improvement
App 20060101355 - Ciplickas; Dennis ; et al. | 2006-05-11 |
Implantation of deuterium in MOS and DRAM devices
App 20050255684 - Koldiaev, Viktor ; et al. | 2005-11-17 |
System and method for product yield prediction
App 20050158888 - Stine, Brian E. ; et al. | 2005-07-21 |
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