loadpatents
name:-0.013599872589111
name:-0.0098428726196289
name:-0.0044949054718018
Paynter; Charles David Patent Filings

Paynter; Charles David

Patent Applications and Registrations

Patent applications and USPTO patent grants for Paynter; Charles David.The latest application filed is for "patch substrate configured as a shield located over a cavity of a board".

Company Profile
4.9.12
  • Paynter; Charles David - Encinitas CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Patch substrate configured as a shield located over a cavity of a board
Grant 11,452,246 - Paynter , et al. September 20, 2
2022-09-20
Patch Substrate Configured As A Shield Located Over A Cavity Of A Board
App 20210307218 - PAYNTER; Charles David ;   et al.
2021-09-30
Package Comprising A Substrate And A High-density Interconnect Integrated Device Coupled To The Substrate
App 20210296246 - LANE; Ryan ;   et al.
2021-09-23
Substrate-embedded Substrate
App 20200020624 - KANG; Kuiwon ;   et al.
2020-01-16
Integrated circuit (IC) module comprising an integrated circuit (IC) package and an interposer with embedded passive components
Grant 10,321,575 - Li , et al.
2019-06-11
Staggered power structure in a power distribution network (PDN)
Grant 10,231,324 - Lane , et al.
2019-03-12
Toroid inductor with reduced electromagnetic field leakage
Grant 10,170,232 - Li , et al. J
2019-01-01
Inductor embedded in a package substrate
Grant 10,008,316 - Fazelpour , et al. June 26, 2
2018-06-26
Method and apparatus for routing die signals using external interconnects
Grant 9,871,012 - Srinivas , et al. January 16, 2
2018-01-16
Toroid Inductor With Reduced Electromagnetic Field Leakage
App 20170125152 - Li; Yue ;   et al.
2017-05-04
Integrated Circuit (ic) Module Comprising An Integrated Circuit (ic) Package And An Interposer With Embedded Passive Components
App 20170064837 - Li; Yue ;   et al.
2017-03-02
Apparatus and methods for shielding differential signal pin pairs
Grant 9,514,966 - Fazelpour , et al. December 6, 2
2016-12-06
Systems and methods for thermal dissipation
Grant 9,484,281 - Lane , et al. November 1, 2
2016-11-01
Systems And Methods For Thermal Dissipation
App 20160049349 - LANE; Ryan David ;   et al.
2016-02-18
Custom Orientation Of Socket Pins To Achieve High Isolation Between Channels Without Adding Extra Reference Pins
App 20150372425 - FAZELPOUR; Siamak ;   et al.
2015-12-24
Staggered Power Structure In A Power Distribution Network (pdn)
App 20150313006 - Lane; Ryan David ;   et al.
2015-10-29
Apparatus And Methods For Shielding Differential Signal Pin Pairs
App 20150294945 - FAZELPOUR; Siamak ;   et al.
2015-10-15
Package on package (PoP) integrated device comprising a redistribution layer
Grant 9,153,560 - Lane , et al. October 6, 2
2015-10-06
Inductor Embedded In A Package Subtrate
App 20150279545 - Fazelpour; Siamak ;   et al.
2015-10-01
PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A REDISTRIBUTION LAYER
App 20150206854 - Lane; Ryan David ;   et al.
2015-07-23
Method And Apparatus For Routing Die Signals Using External Interconnects
App 20140061642 - Srinivas; Vaishnav ;   et al.
2014-03-06

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