loadpatents
name:-0.033031940460205
name:-0.033314943313599
name:-0.0016119480133057
Pawlak; Bartlomiej Jan Patent Filings

Pawlak; Bartlomiej Jan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pawlak; Bartlomiej Jan.The latest application filed is for "vertical fet with self-aligned source/drain regions and gate length based on channel epitaxial growth process".

Company Profile
1.31.29
  • Pawlak; Bartlomiej Jan - Leuven BE
  • Pawlak; Bartlomiej Jan - Heverlee BE
  • Pawlak; Bartlomiej Jan - Lueven BE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Micro-LED display assembly
Grant 10,770,440 - England , et al. Sep
2020-09-08
Tunneling field effect transistor
Grant 10,340,369 - Pawlak
2019-07-02
Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
Grant 10,304,833 - Suvarna , et al.
2019-05-28
Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process
Grant 10,236,379 - Bentley , et al.
2019-03-19
Vertical Fet With Self-aligned Source/drain Regions And Gate Length Based On Channel Epitaxial Growth Process
App 20180331213 - Bentley; Steven ;   et al.
2018-11-15
Amorphization induced metal-silicon contact formation
Grant 10,128,114 - Pawlak November 13, 2
2018-11-13
Micro-led Display Assembly
App 20180269191 - ENGLAND; Luke ;   et al.
2018-09-20
Semiconductor device with gate inside U-shaped channel and methods of making such a device
Grant 10,020,395 - Pawlak July 10, 2
2018-07-10
Texturing Of Silicon Surface With Direct-self Assembly Patterning
App 20180053662 - PAWLAK; Bartlomiej Jan ;   et al.
2018-02-22
Tunneling Field Effect Transistor
App 20180006143 - Pawlak; Bartlomiej Jan
2018-01-04
Tunneling field effect transistor and methods of making such a transistor
Grant 9,793,384 - Pawlak October 17, 2
2017-10-17
Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device
Grant 9,741,847 - Pawlak August 22, 2
2017-08-22
Semiconductor device comprising a multi-layer channel region
Grant 9,716,177 - Pawlak , et al. July 25, 2
2017-07-25
Methods of making source/drain regions positioned inside U-shaped semiconductor material using source/drain placeholder structures
Grant 9,711,644 - Pawlak July 18, 2
2017-07-18
Horizontal gate all around nanowire transistor bottom isolation
Grant 9,704,962 - Pawlak July 11, 2
2017-07-11
Horizontal Gate All Around Nanowire Transistor Bottom Isolation
App 20170179248 - PAWLAK; Bartlomiej Jan
2017-06-22
Methods Of Forming A Contact Structure For A Vertical Channel Semiconductor Device And The Resulting Device
App 20170154994 - Pawlak; Bartlomiej Jan
2017-06-01
Method of fabricating FinFET device and structure thereof
Grant 9,653,593 - Pawlak May 16, 2
2017-05-16
Amophization Induced Metal-silicon Contact Formation
App 20170098544 - PAWLAK; Bartlomiej Jan
2017-04-06
Methods of forming metal source/drain contact structures for semiconductor devices with gate all around channel structures
Grant 9,601,379 - Pawlak , et al. March 21, 2
2017-03-21
Methods Of Making Source/drain Regions Positioned Inside U-shaped Semiconductor Material Using Source/drain Placeholder Structures
App 20170077301 - Pawlak; Bartlomiej Jan
2017-03-16
Semiconductor Device With Gate Inside U-shaped Channel And Methods Of Making Such A Device
App 20170077297 - Pawlak; Bartlomiej Jan
2017-03-16
Stress relaxed buffer layer on textured silicon surface
Grant 9,558,943 - Pawlak January 31, 2
2017-01-31
Stress Relaxed Buffer Layer On Textured Silicon Surface
App 20170018421 - PAWLAK; Bartlomiej Jan
2017-01-19
Interdigitated electrode formation
Grant 9,419,154 - Pawlak , et al. August 16, 2
2016-08-16
Methods of forming substrates comprised of different semiconductor materials and the resulting device
Grant 9,368,578 - Pawlak , et al. June 14, 2
2016-06-14
Semiconductor Device Comprising A Multi-layer Channel Region
App 20160133740 - Pawlak; Bartlomiej Jan ;   et al.
2016-05-12
Tunneling Field Effect Transistor And Methods Of Making Such A Transistor
App 20160099343 - Pawlak; Bartlomiej Jan
2016-04-07
Methods of forming a channel region for a semiconductor device by performing a triple cladding process
Grant 9,263,555 - Pawlak , et al. February 16, 2
2016-02-16
Methods Of Forming A Channel Region For A Semiconductor Device By Performing A Triple Cladding Process
App 20160005834 - Pawlak; Bartlomiej Jan ;   et al.
2016-01-07
Methods of forming a nanowire device with a gate-all-around-channel configuration and the resulting nanowire device
Grant 9,166,025 - Pawlak October 20, 2
2015-10-20
Fin pitch scaling and active layer isolation
Grant 9,076,842 - Jacob , et al. July 7, 2
2015-07-07
Fin Pitch Scaling And Active Layer Isolation
App 20150061014 - JACOB; Ajey Poovannummoottil ;   et al.
2015-03-05
Fabrication method for interdigitated back contact photovoltaic cells
Grant 8,900,891 - Pawlak , et al. December 2, 2
2014-12-02
Methods Of Forming Substrates Comprised Of Different Semiconductor Materials And The Resulting Device
App 20140217467 - Pawlak; Bartlomiej Jan ;   et al.
2014-08-07
Interdigitated Electrode Formation
App 20140174526 - Pawlak; Bartlomiej Jan ;   et al.
2014-06-26
Methods of forming fins for a FinFET semiconductor device using a mandrel oxidation process
Grant 8,716,156 - Pawlak , et al. May 6, 2
2014-05-06
Method of Fabricating FinFET Device and Structure Thereof
App 20130126951 - Pawlak; Bartlomiej Jan
2013-05-23
Method of fabricating finfet device
Grant 8,357,569 - Pawlak January 22, 2
2013-01-22
Semiconductor substrate with solid phase epitaxial regrowth with reduced junction leakage and method of producing same
Grant 8,187,959 - Pawlak , et al. May 29, 2
2012-05-29
Fabrication Method For Interdigitated Back Contact Photovoltaic Cells
App 20110303280 - Pawlak; Bartlomiej Jan ;   et al.
2011-12-15
Method Of Fabricating Finfet Device
App 20110073919 - Pawlak; Bartlomiej Jan
2011-03-31
Field effect transistor and method of manufacturing a field effect transistor
Grant 7,615,430 - Pawlak November 10, 2
2009-11-10
Method for junction formation in a semiconductor device and the semiconductor device made thereof
Grant 7,582,547 - Pawlak September 1, 2
2009-09-01
Semiconductor Substrate With Solid Phase Epitaxial Regrowth With Reduced Junction Leakage And Method Of Producing Same
App 20090140242 - Pawlak; Bartlomiej Jan ;   et al.
2009-06-04
Method of manufacturing a semiconductor device including dopant introduction
Grant 7,491,616 - Pawlak February 17, 2
2009-02-17
Method of Manufacturing a Semiconductor Device and Semiconductor Device Obtainable with Such a Method
App 20080105922 - Pawlak; Bartlomiej Jan
2008-05-08
Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
Grant 7,348,229 - Pawlak , et al. March 25, 2
2008-03-25
Method For Forming Doped Metal-semiconductor Compound Regions
App 20080057685 - Pawlak; Bartlomiej Jan ;   et al.
2008-03-06
Method For Junction Formation In A Semiconductor Device And The Semiconductor Device Made Thereof
App 20080057683 - Pawlak; Bartlomiej Jan
2008-03-06
Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method
Grant 7,326,620 - Pawlak February 5, 2
2008-02-05
Field effect transistor and method of manufacturing a field effect transistor
App 20070184620 - Pawlak; Bartlomiej Jan
2007-08-09
Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
App 20070173041 - Pawlak; Bartlomiej Jan
2007-07-26
Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
App 20070105291 - Pawlak; Bartlomiej Jan ;   et al.
2007-05-10
Method of manufacturing a semiconductor on a silicon on insulator (SOI) substrate using solid epitaxial regrowth (SPER) and semiconductor device made thereby
Grant 7,122,452 - Pawlak October 17, 2
2006-10-17
Formation of junctions and silicides with reduced thermal budget
App 20060141728 - Pawlak; Bartlomiej Jan
2006-06-29
Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method
App 20050236663 - Pawlak, Bartlomiej Jan
2005-10-27
Method of manufacturing a semiconductor on a silicon on insulator (SOI) substrate using solid epitaxial regrowth (SPER) and semiconductor device made thereby
App 20050227421 - Pawlak, Bartlomiej Jan
2005-10-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed