Paul; Gael
Patent Applications and Registrations
Patent applications and USPTO patent grants for Paul; Gael.The latest application filed is for "system and method for licensing and for measuring use of an ip block".
- Paul; Gael - Bouc Bel Air FR
- PAUL; Gael - AIX EN PROVENCE FR
- Paul; Gael - Palo Alto CA
- Paul; Gael - Menlo Park CA
| Patent | Date |
|---|---|
| System and method for authenticating and IP licensing of hardware modules Grant 11,023,621 - Torres , et al. June 1, 2 | 2021-06-01 |
| System And Method For Licensing And For Measuring Use Of An Ip Block App 20200372128 - TORRES; Lionel ; et al. | 2020-11-26 |
| Automated bottom-up and top-down partitioned design synthesis Grant 10,296,689 - Bakshi , et al. | 2019-05-21 |
| System and method for authenticating and IP licensing of hardware modules App 20180196965 - TORRES; Lionel ; et al. | 2018-07-12 |
| Circuit Design and Optimization App 20160188774 - Adya; Saurabh ; et al. | 2016-06-30 |
| Methods and apparatuses for circuit design and optimization Grant 9,280,632 - Adya , et al. March 8, 2 | 2016-03-08 |
| Automated Bottom-Up and Top-Down Partitioned Design Synthesis App 20150012898 - Bakshi; Smita ; et al. | 2015-01-08 |
| Asychronous system analysis Grant 8,661,378 - Manohar , et al. February 25, 2 | 2014-02-25 |
| Reset mechanism conversion Grant 8,443,315 - Manohar , et al. May 14, 2 | 2013-05-14 |
| Methods and Apparatuses for Circuit Design and Optimization App 20130061195 - Adya; Saurabh ; et al. | 2013-03-07 |
| Methods and apparatuses for circuit design and optimization Grant 8,307,315 - Adya , et al. November 6, 2 | 2012-11-06 |
| Multi-clock asynchronous logic circuits Grant 8,301,933 - Manohar , et al. October 30, 2 | 2012-10-30 |
| Token enhanced asynchronous conversion of synchonous circuits Grant 8,234,607 - Ekanayake , et al. July 31, 2 | 2012-07-31 |
| Reset Mechanism Conversion App 20120180012 - Manohar; Rajit ; et al. | 2012-07-12 |
| Reset mechanism conversion Grant 8,161,435 - Manohar , et al. April 17, 2 | 2012-04-17 |
| Automated Bottom-Up and Top-Down Partitioned Design Synthesis App 20120089956 - Bakshi; Smita ; et al. | 2012-04-12 |
| Logic performance in cyclic structures Grant 8,104,004 - Paul , et al. January 24, 2 | 2012-01-24 |
| Automated bottom-up and top-down partitioned design synthesis Grant 8,082,138 - Bakshi , et al. December 20, 2 | 2011-12-20 |
| Asynchronous circuit representation of synchronous circuit with asynchronous inputs Grant 7,982,502 - Manohar , et al. July 19, 2 | 2011-07-19 |
| Asychronous System Analysis App 20110078644 - Manohar; Rajit ; et al. | 2011-03-31 |
| Token Enhanced Asynchronous Conversion Of Synchonous Circuits App 20110066986 - Ekanayake; Virantha ; et al. | 2011-03-17 |
| Asynchronous Circuit Representation Of Synchronous Circuit With Asynchronous Inputs App 20110062991 - Manohar; Rajit ; et al. | 2011-03-17 |
| Multi-clock Asynchronous Logic Circuits App 20110066873 - Manohar; Rajit ; et al. | 2011-03-17 |
| Reset Mechanism Conversion App 20110016439 - Manohar; Rajit ; et al. | 2011-01-20 |
| Methods And Apparatuses For Circuit Design And Optimization App 20100199234 - Adya; Saurabh ; et al. | 2010-08-05 |
| Logic Performance In Cyclic Structures App 20090201044 - Paul; Gael ; et al. | 2009-08-13 |
| Skew reduction for generated clocks Grant 7,500,205 - Paul , et al. March 3, 2 | 2009-03-03 |
| Skew reduction for generated clocks App 20060129961 - Paul; Gael ; et al. | 2006-06-15 |
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