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Processor Core Design Optimized for Machine Learning Applications
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Security within a software-defined infrastructure
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Security within a software-defined infrastructure
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Invalidation of shared memory in a virtual environment
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Shared Memory In A Virtual Environment
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Invalidation of shared memory in a virtual environment
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Shared memory in a virtual environment
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Software Patch Management Incorporating Sentiment Analysis
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Software patch management incorporating sentiment analysis
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Software patch management incorporating sentiment analysis
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Security within a software-defined infrastructure
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Identifying and tracking frequently accessed registers in a processor
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Cache Memory Transaction Shielding Via Prefetch Suppression
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Shared Memory In A Virtual Environment
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Invalidation Of Shared Memory In A Virtual Environment
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Capability-based abstraction of software-defined infrastructure
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Identifying And Tracking Frequently Accessed Registers In A Processor
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Outcome-based Software-defined Infrastructure
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Security Within A Software-defined Infrastructure
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Memory transaction having implicit ordering effects
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Memory transaction having implicit ordering effects
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Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction
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Memory Transaction Having Implicit Ordering Effects
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Techniques for Increasing Vector Processing Utilization and Efficiency Through Vector Lane Predication Prediction
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Seamless interface for multi-threaded core accelerators
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Method and apparatus for securing communications along ac power lines
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