Patterson; Cameron D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patterson; Cameron D..The latest application filed is for "hardware-facilitated secure software execution environment".

Company Profile

0.17.0

Patterson; Cameron D. - Blacksburg VA
Patterson; Cameron D. - Longmont CO
Patterson; Cameron D. - Los Gatos CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hardware-facilitated secure software execution environment Grant 8,473,754 - Jones , et al. June 25, 2	2013-06-25
Method and apparatus for dynamically connecting modules in a programmable device Grant 7,669,168 - Patterson February 23, 2	2010-02-23
Method and system for identifying essential configuration bits Grant 7,406,673 - Patterson , et al. July 29, 2	2008-07-29
Method and system for generating a bitstream view of a design Grant 7,343,578 - Patterson , et al. March 11, 2	2008-03-11
Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA Grant 7,249,010 - Sundararajan , et al. July 24, 2	2007-07-24
Core template package for creating run-time reconfigurable cores Grant 7,143,418 - Patterson November 28, 2	2006-11-28
Integration of a run-time parameterizable core with a static circuit design Grant 7,139,995 - James-Roxby , et al. November 21, 2	2006-11-21
Method and apparatus for dynamically connecting modules in a programmable logic device Grant 7,124,391 - Patterson October 17, 2	2006-10-17
Field programmable gate array (FPGA) configuration data path for module communication Grant 7,080,226 - Patterson July 18, 2	2006-07-18
Parameterizable and reconfigurable debugger core generators Grant 6,802,026 - Patterson , et al. October 5, 2	2004-10-05
Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices Grant 6,725,441 - Keller , et al. April 20, 2	2004-04-20
Hetergeneous method for determining module placement in FPGAs Grant 6,457,164 - Hwang , et al. September 24, 2	2002-09-24
Method for structured layout in a hardware description language Grant 6,430,732 - Hwang , et al. August 6, 2	2002-08-06
Method for remapping logic modules to resources of a programmable gate array Grant 6,408,422 - Hwang , et al. June 18, 2	2002-06-18
Heterogeneous method for determining module placement in FPGAs Grant 6,243,851 - Hwang , et al. June 5, 2	2001-06-05
Method for constraining circuit element positions in structured layouts Grant 6,237,129 - Patterson , et al. May 22, 2	2001-05-22

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