loadpatents
name:-0.020174980163574
name:-0.017126083374023
name:-0.016236066818237
Patten; Richard Patent Filings

Patten; Richard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patten; Richard.The latest application filed is for "package stacking using chip to wafer bonding".

Company Profile
11.14.20
  • Patten; Richard - Langquaid DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Wafer level package structure with internal conductive layer
Grant 11,424,209 - Albers , et al. August 23, 2
2022-08-23
Package Stacking Using Chip To Wafer Bonding
App 20220108976 - SEIDEMANN; Georg ;   et al.
2022-04-07
Package stacking using chip to wafer bonding
Grant 11,239,199 - Seidemann , et al. February 1, 2
2022-02-01
Microelectronic Packages With High Integration Microelectronic Dice Stack
App 20210035950 - PATTEN; Richard
2021-02-04
Method, apparatus and system to interconnect packaged integrated circuit dies
Grant 10,910,347 - She , et al. February 2, 2
2021-02-02
Microelectronic packages with high integration microelectronic dice stack
Grant 10,872,881 - Patten December 22, 2
2020-12-22
Semiconductor die package with more than one hanging die
Grant 10,854,590 - Albers , et al. December 1, 2
2020-12-01
Integrated circuit packages including an optical redistribution layer
Grant 10,816,742 - Seidemann , et al. October 27, 2
2020-10-27
Wafer Level Package Structure With Internal Conductive Layer
App 20200273832 - ALBERS; Sven ;   et al.
2020-08-27
Microelectronic Packages With High Integration Microelectronic Dice Stack
App 20200219844 - PATTEN; Richard
2020-07-09
Semiconductor Die Package With More Than One Hanging Die
App 20200176436 - ALBERS; Sven ;   et al.
2020-06-04
Wafer level package structure with internal conductive layer
Grant 10,672,731 - Albers , et al.
2020-06-02
Microelectronic packages with high integration microelectronic dice stack
Grant 10,622,333 - Patten
2020-04-14
Novel Wafer Level Chip Scale Package (wlcsp), Flip-chip Chip Scale Package (fccsp), And Fan Out Shielding Concepts
App 20200098698 - PATTEN; Richard ;   et al.
2020-03-26
Method, Apparatus And System To Interconnect Packaged Integrated Circuit Dies
App 20190341372 - She; Yong ;   et al.
2019-11-07
Fan Out Packaging Pop Mechanical Attach Method
App 20190312016 - O'Sullivan; David ;   et al.
2019-10-10
Microelectronic package with illuminated backside exterior
Grant 10,411,000 - Dittes , et al. Sept
2019-09-10
Method, apparatus and system to interconnect packaged integrated circuit dies
Grant 10,396,055 - She , et al. A
2019-08-27
Optical Fiber Connection On Package Edge
App 20190121041 - Albers; Sven ;   et al.
2019-04-25
Microelectronic Packages With High Integration Microelectronic Dice Stack
App 20190109114 - PATTEN; Richard
2019-04-11
Integrated circuit package having wirebonded multi-die stack
Grant 10,249,598 - Meyer , et al.
2019-04-02
Integrated Circuit Packages Including An Optical Redistribution Layer
App 20190072732 - Seidemann; Georg ;   et al.
2019-03-07
Integrated circuit packages including an optical redistribution layer
Grant 10,209,466 - Seidemann , et al. Feb
2019-02-19
Method, Apparatus And System To Interconnect Packaged Integrated Circuit Dies
App 20190019777 - SHE; Yong ;   et al.
2019-01-17
Wafer Level Package Structure With Internal Conductive Layer
App 20180358317 - ALBERS; Sven ;   et al.
2018-12-13
Package Stacking Using Chip To Wafer Bonding
App 20180331070 - SEIDEMANN; Georg ;   et al.
2018-11-15
Integrated Circuit Package Having Wirebonded Multi-die Stack
App 20180315737 - Meyer; Thorsten ;   et al.
2018-11-01
Integrated Circuit Package Having Wirebonded Multi-die Stack
App 20180197840 - Meyer; Thorsten ;   et al.
2018-07-12
Integrated circuit package having wirebonded multi-die stack
Grant 9,972,601 - Meyer , et al. May 15, 2
2018-05-15
Electronic device package
Grant 9,859,255 - Yoon , et al. January 2, 2
2018-01-02
Microelectronic Package with Illuminated Backside Exterior
App 20170284636 - Dittes; Marc Stephan ;   et al.
2017-10-05
Integrated Circuit Packages Including An Optical Redistribution Layer
App 20170285280 - Seidemann; Georg ;   et al.
2017-10-05
Flip-chip Package With Thermal Dissipation Layer
App 20170178999 - Patten; Richard ;   et al.
2017-06-22
Integrated Circuit Package Having Wirebonded Multi-die Stack
App 20160276311 - Meyer; Thorsten ;   et al.
2016-09-22
Company Registrations

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed