Patil; Nishant

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patil; Nishant.The latest application filed is for "modifying machine learning models to improve locality".

Company Profile

5.11.9

Patil; Nishant - Sunnyvale CA
Patil; Nishant - Mountain View CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Modifying Machine Learning Models To Improve Locality App 20220172060 - Yoon; Doe Hyun ; et al.	2022-06-02
Asymmetric Data Communication For Host-device Interface App 20220083493 - Patil; Nishant ; et al.	2022-03-17
Modifying machine learning models to improve locality Grant 11,263,529 - Yoon , et al. March 1, 2	2022-03-01
Asymmetric data communication for host-device interface Grant 11,188,494 - Patil , et al. November 30, 2	2021-11-30
Reconfigurable Computing Pods Using Optical Networks App 20210286656 - Patil; Nishant ; et al.	2021-09-16
Managing Processing System Efficiency App 20210224129 - Cheng; Liqun ; et al.	2021-07-22
Reconfigurable computing pods using optical networks Grant 11,042,416 - Patil , et al. June 22, 2	2021-06-22
Managing processing system efficiency Grant 10,908,964 - Cheng , et al. February 2, 2	2021-02-02
Asymmetric Data Communication For Host-device Interface App 20200371984 - Patil; Nishant ; et al.	2020-11-26
Bandwidth Allocation In Asymmetrical Switch Topologies App 20200341931 - Makhija; Pankaj ; et al.	2020-10-29
Reconfigurable Computing Pods Using Optical Networks App 20200285524 - Patil; Nishant ; et al.	2020-09-10
Modifying Machine Learning Models To Improve Locality App 20200117999 - Yoon; Doe Hyun ; et al.	2020-04-16
Managing Processing System Efficiency App 20190155658 - Cheng; Liqun ; et al.	2019-05-23
Optimized matrix multiplication using vector multiplication of interleaved matrix values Grant 10,073,817 - Patil , et al. September 11, 2	2018-09-11
Optimized matrix multiplication using vector multiplication of interleaved matrix values Grant 9,830,303 - Patil , et al. November 28, 2	2017-11-28
Optimized matrix multiplication using vector multiplication of interleaved matrix values Grant 9,645,974 - Patil , et al. May 9, 2	2017-05-09
Multi-level logical block address (LBA) mapping table for solid state Grant 9,218,294 - Patil , et al. December 22, 2	2015-12-22
Write processing for unchanged data with new metadata Grant 8,832,539 - Patil , et al. September 9, 2	2014-09-09
System and method for analyzing a nanotube logic circuit Grant 8,065,634 - Patil , et al. November 22, 2	2011-11-22
Nanotube logic circuits Grant 7,911,234 - Patil , et al. March 22, 2	2011-03-22

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