Pathirane; Chiloda Ashan Senerath
Patent Applications and Registrations
Patent applications and USPTO patent grants for Pathirane; Chiloda Ashan Senerath.The latest application filed is for "instruction fusion".
- Pathirane; Chiloda Ashan Senerath - Cambridge GB
- Pathirane; Chiloda Ashan Senerath - Haverhill N/A GB
| Patent | Date |
|---|---|
| Fusion of instructions by delaying handling of a partial subset of a fusible group of instructions Grant 10,579,389 - Caulfield , et al. | 2020-03-03 |
| Executing debug program instructions on a target apparatus processing pipeline Grant 9,710,359 - Pathirane , et al. July 18, 2 | 2017-07-18 |
| Parallel lookup in first and second value stores Grant 9,665,494 - Skillman , et al. May 30, 2 | 2017-05-30 |
| Malfunction escalation Grant 9,658,919 - Pathirane , et al. May 23, 2 | 2017-05-23 |
| Branch target address cache using hashed fetch addresses Grant 9,645,824 - Vasekin , et al. May 9, 2 | 2017-05-09 |
| Instruction Fusion App 20170123808 - CAULFIELD; Ian Michael ; et al. | 2017-05-04 |
| Memory built-in self-test for a data processing apparatus Grant 9,449,717 - Becker , et al. September 20, 2 | 2016-09-20 |
| Memory Built-in Self-test For A Data Processing Apparatus App 20150371718 - BECKER; Alan Jeremy ; et al. | 2015-12-24 |
| Executing Debug Program Instructions On A Target Apparatus Processing Pipeline App 20150363293 - PATHIRANE; Chiloda Ashan Senerath ; et al. | 2015-12-17 |
| Parallel Lookup In First And Second Value Stores App 20150363321 - SKILLMAN; Allan John ; et al. | 2015-12-17 |
| Malfunction Escalation App 20150355962 - PATHIRANE; Chiloda Ashan Senerath ; et al. | 2015-12-10 |
| Instruction fetching following changes in program flow Grant 8,966,228 - Craske , et al. February 24, 2 | 2015-02-24 |
| Branch Target Address Cache Using Hashed Fetch Addresses App 20140122846 - VASEKIN; Vladimir ; et al. | 2014-05-01 |
| Debugging a multiprocessor system that switches between a locked mode and a split mode Grant 8,108,730 - Pathirane , et al. January 31, 2 | 2012-01-31 |
| Initialisation of a pipelined processor Grant 8,055,888 - Pathirane , et al. November 8, 2 | 2011-11-08 |
| Auxiliary circuit structure in a split-lock dual processor system Grant 8,051,323 - Pathirane , et al. November 1, 2 | 2011-11-01 |
| Power efficient interrupt detection Grant 8,015,337 - Kocherry , et al. September 6, 2 | 2011-09-06 |
| Auxiliary circuit structure in a split-lock dual processor system App 20110179308 - Pathirane; Chiloda Ashan Senerath ; et al. | 2011-07-21 |
| Data processing reset operations App 20110179255 - Pathirane; Chiloda Ashan Senerath ; et al. | 2011-07-21 |
| Debugging a multiprocessor system that switches between a locked mode and a split mode App 20110179309 - Pathirane; Chiloda Ashan Senerath ; et al. | 2011-07-21 |
| Instruction fetching following changes in program flow App 20100241832 - Craske; Simon John ; et al. | 2010-09-23 |
| Power efficient interrupt detection App 20100241777 - Kocherry; Mittu Xavier ; et al. | 2010-09-23 |
| Initialisation of a pipelined processor App 20090222649 - Pathirane; Chiloda Ashan Senerath ; et al. | 2009-09-03 |
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