Pathak; Piyush

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pathak; Piyush.The latest application filed is for "method, system and program product for identifying anomalies in integrated circuit design layouts".

Company Profile

1.7.5

Pathak; Piyush - Fremont CA
Pathak; Piyush - Sunnyvale CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Three-dimensional pattern risk scoring Grant 10,311,186 - Bravo , et al.	2019-06-04
Method, system and program product for identifying anomalies in integrated circuit design layouts Grant 10,055,535 - Pathak , et al. August 21, 2	2018-08-21
Method, System And Program Product For Identifying Anomalies In Integrated Circuit Design Layouts App 20180089357 - PATHAK; Piyush ; et al.	2018-03-29
Three-dimensional Pattern Risk Scoring App 20170293704 - BRAVO; Jaime ; et al.	2017-10-12
Detecting hotspots using machine learning on diffraction patterns Grant 9,626,459 - Agarwal , et al. April 18, 2	2017-04-18
Detecting Hotspots Using Machine Learning On Diffraction Patterns App 20150213374 - Agarwal; Kanak B. ; et al.	2015-07-30
Layout pattern correction for integrated circuits Grant 8,898,606 - Abou Ghaida , et al. November 25, 2	2014-11-25
Methods of modifying a physical design of an electrical circuit used in the manufacture of a semiconductor device Grant 8,739,077 - Pathak , et al. May 27, 2	2014-05-27
Pattern based method for identifying design for manufacturing improvement in a semiconductor device Grant 8,656,336 - Pathak , et al. February 18, 2	2014-02-18
Pattern Based Method For Identifying Design For Manufacturing Improvement In A Semiconductor Device App 20130227498 - Pathak; Piyush ; et al.	2013-08-29

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