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name:-0.013231992721558
name:-0.0082659721374512
name:-0.0005800724029541
Patella; Benjamin J. Patent Filings

Patella; Benjamin J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patella; Benjamin J..The latest application filed is for "count calibration for synchronous data transfer between clock domains".

Company Profile
0.7.9
  • Patella; Benjamin J. - Fort Collins CO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Edge calibration for synchronous data transfer between clock domains
Grant 7,558,317 - Fischer , et al. July 7, 2
2009-07-07
Adaptable data path for synchronous data transfer between clock domains
Grant 7,477,712 - Fischer , et al. January 13, 2
2009-01-13
Count calibration for synchronous data transfer between clock domains
Grant 7,401,245 - Fischer , et al. July 15, 2
2008-07-15
System and method for dynamically varying a clock signal
Grant 7,394,301 - Fetzer , et al. July 1, 2
2008-07-01
Adaptable data path for synchronous data transfer between clock domains
App 20060245529 - Fischer; Timothy C. ;   et al.
2006-11-02
Edge calibration for synchronous data transfer between clock domains
App 20060244642 - Fischer; Timothy C. ;   et al.
2006-11-02
Count calibration for synchronous data transfer between clock domains
App 20060248367 - Fischer; Timothy C. ;   et al.
2006-11-02
Detection of bit errors in maskable content addressable memories
Grant 7,100,097 - Patella , et al. August 29, 2
2006-08-29
System and method for dynamically varying a clock signal
App 20050231259 - Fetzer, Eric S. ;   et al.
2005-10-20
Circuit and associated methodology
Grant 6,946,877 - Patella , et al. September 20, 2
2005-09-20
System and method for dynamically varying a clock signal
Grant 6,927,605 - Fetzer , et al. August 9, 2
2005-08-09
Circuit and associated methodology
App 20050127951 - Patella, Benjamin J. ;   et al.
2005-06-16
System and method for dynamically varying a clock signal
App 20050099210 - Fetzer, Eric S. ;   et al.
2005-05-12
System and method for evaluating the speed of a circuit
App 20050007154 - Patella, Benjamin J. ;   et al.
2005-01-13
Detection of bit errors in content addressable memories
App 20040015753 - Patella, Benjamin J. ;   et al.
2004-01-22
Detection of bit errors in maskable content addressable memories
App 20040015752 - Patella, Benjamin J. ;   et al.
2004-01-22

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