Patel; Rakesh H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patel; Rakesh H..The latest application filed is for "distributing power with through-silicon-vias".

Company Profile

0.90.27

Patel; Rakesh H. - Cupertino CA US
Patel; Rakesh H - Cupertino CA
Patel; Rakesh H. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-tuning high speed transceiver for IC wireline channel Grant 9,160,405 - Vareljian , et al. October 13, 2	2015-10-13
Memory circuit including memory devices, a freeze circuit and a test switch Grant 9,111,641 - Patel , et al. August 18, 2	2015-08-18
Stacked die network-on-chip for FPGA Grant 8,863,065 - Chow , et al. October 14, 2	2014-10-14
Distributing power with through-silicon-vias Grant 8,835,224 - White , et al. September 16, 2	2014-09-16
Heterogeneous transceiver architecture for wide range programmability of programmable logic devices Grant 8,787,352 - Shumarayev , et al. July 22, 2	2014-07-22
Stacked die network-on-chip for FPGA Grant 8,719,753 - Chow , et al. May 6, 2	2014-05-06
Digital equalizer for high-speed serial communications Grant 8,654,898 - Bereza , et al. February 18, 2	2014-02-18
3T device based memory circuits and arrays Grant 8,599,598 - Patel , et al. December 3, 2	2013-12-03
Stacked semiconductor substrates Grant 8,557,636 - Patel October 15, 2	2013-10-15
Method and apparatus for multi-mode clock data recovery Grant 8,537,954 - Shumarayev , et al. September 17, 2	2013-09-17
Distributing Power With Through-silicon-vias App 20130011965 - White; Thomas Henry ; et al.	2013-01-10
Distributing power with through-silicon-vias Grant 8,344,496 - White , et al. January 1, 2	2013-01-01
Stacked semiconductor substrates Grant 8,294,252 - Patel October 23, 2	2012-10-23
Phase-locked loop circuitry with multiple voltage-controlled oscillators Grant 8,130,044 - Bereza , et al. March 6, 2	2012-03-06
MEMS switching device and conductive bridge device based circuits Grant 8,130,559 - Patel , et al. March 6, 2	2012-03-06
Voltage-controlled oscillator methods and apparatus Grant 8,120,429 - Hoang , et al. February 21, 2	2012-02-21
Zero-delay serial communications circuitry for serial interconnects Grant 8,014,480 - Zhuang , et al. September 6, 2	2011-09-06
Heterogeneous Transceiver Architecture For Wide Range Programmability Of Programmable Logic Devices App 20110211621 - Shumarayev; Sergey ; et al.	2011-09-01
Circuit distribution to multiple integrated circuits Grant 8,000,106 - Patel August 16, 2	2011-08-16
Heterogeneous transceiver architecture for wide range programmability of programmable logic devices Grant 7,940,814 - Shumarayev , et al. May 10, 2	2011-05-10
Clock signal circuitry for multi-channel data signaling Grant 7,812,659 - Shumarayev , et al. October 12, 2	2010-10-12
Circuitry for providing programmable decision feedback equalization Grant 7,804,892 - Shumarayev , et al. September 28, 2	2010-09-28
Signal adjustment receiver circuitry Grant 7,733,982 - Wong , et al. June 8, 2	2010-06-08
Voltage-controlled oscillator methods and apparatus Grant 7,728,674 - Hoang , et al. June 1, 2	2010-06-01
Method And Apparatus For Multi-mode Clock Data Recovery App 20100119024 - Shumarayev; Sergey Y. ; et al.	2010-05-13
Stacked die network-on-chip for FPGA Grant 7,701,252 - Chow , et al. April 20, 2	2010-04-20
Multiple data rates in integrated circuit device serial interface Grant 7,698,482 - Venkata , et al. April 13, 2	2010-04-13
Systems and methods for simulating link performance Grant 7,693,691 - Tao , et al. April 6, 2	2010-04-06
Method and apparatus for multi-mode clock data recovery Grant 7,680,232 - Shumarayev , et al. March 16, 2	2010-03-16
Heterogeneous Transceiver Architecture For Wide Range Programmability Of Programmable Logic Devices App 20100058099 - Shumarayev; Sergey ; et al.	2010-03-04
Apparatus for all-digital serializer-de-serializer and associated methods Grant 7,656,323 - Bereza , et al. February 2, 2	2010-02-02
Programmable logic device with serial interconnect Grant 7,646,217 - Venkata , et al. January 12, 2	2010-01-12
Phase-locked Loop Circuitry With Multiple Voltage-controlled Oscillators App 20090315627 - Bereza; William W. ; et al.	2009-12-24
Apparatus For Power Consumption Reduction In Programmable Logic Devices And Associated Methods App 20090302887 - Kwasniewski; Tad ; et al.	2009-12-10
Signal Adjustment Receiver Circuitry App 20090285275 - Wong; Wilson ; et al.	2009-11-19
Signal Adjustment Receiver Circuitry App 20090284292 - Wong; Wilson ; et al.	2009-11-19
Digital Equalizer For High-speed Serial Communications App 20090279597 - Bereza; William W. ; et al.	2009-11-12
Heterogeneous transceiver architecture for wide range programmability of programmable logic devices Grant 7,616,657 - Shumarayev , et al. November 10, 2	2009-11-10
Flexible signal detect for programmable logic device serial interface Grant 7,589,651 - Shumarayev , et al. September 15, 2	2009-09-15
Signal adjustment receiver circuitry Grant 7,590,174 - Wong , et al. September 15, 2	2009-09-15
Modular serial interface in programmable logic device Grant 7,590,207 - Shumarayev , et al. September 15, 2	2009-09-15
Sample and load scheme for observability internal nodes in a PLD Grant RE40,894 - Patel , et al. September 1, 2	2009-09-01
High-speed serial data transmitter architecture Grant 7,557,615 - Tran , et al. July 7, 2	2009-07-07
Comparator offset cancellation assisted by PLD resources Grant 7,541,857 - Wong , et al. June 2, 2	2009-06-02
Multiple data rates in programmable logic device serial interface Grant 7,538,578 - Venkata , et al. May 26, 2	2009-05-26
Wide range and dynamically reconfigurable clock data recovery architecture App 20090122939 - Hoang; Tim Tri ; et al.	2009-05-14
Programmable logic device architecture for accommodating specialized circuitry Grant 7,525,340 - Shumarayev , et al. April 28, 2	2009-04-28
Capacitance switch circuitry for digitally controlled oscillators Grant 7,474,167 - Zhuang , et al. January 6, 2	2009-01-06
Apparatus For All-digital Serializer-de-serializer And Associated Methods App 20080298476 - Bereza; William W. ; et al.	2008-12-04
Next generation 8B10B architecture Grant 7,436,210 - Venkata , et al. October 14, 2	2008-10-14
Phase lock loop and method for operating the same Grant 7,355,462 - Wong , et al. April 8, 2	2008-04-08
Integrated circuit output driver circuitry with programmable preemphasis Grant 7,307,446 - Shumarayev , et al. December 11, 2	2007-12-11
Clock circuitry for programmable logic devices Grant 7,304,498 - Bereza , et al. December 4, 2	2007-12-04
Methods and apparatus to DC couple LVDS driver to CML levels Grant 7,304,494 - Wong , et al. December 4, 2	2007-12-04
Heterogeneous transceiver architecture for wide range programmability of programmable logic devices App 20070237186 - Shumarayev; Sergey ; et al.	2007-10-11
Programmable Logic Device With Serial Interconnect App 20070188189 - Venkata; Ramanand ; et al.	2007-08-16
Signal adjustment receiver circuitry App 20070140387 - Wong; Wilson ; et al.	2007-06-21
Next generation 8B10B architecture App 20070139232 - Venkata; Ramanand ; et al.	2007-06-21
Programmable logic device architecture for accommodating specialized circuitry App 20070063733 - Shumarayev; Sergey Y. ; et al.	2007-03-22
Next generation 8B10B architecture Grant 7,183,797 - Venkata , et al. February 27, 2	2007-02-27
Clock circuitry for programmable logic devices App 20070019766 - Bereza; William W. ; et al.	2007-01-25
Multiple data rates in programmable logic device serial interface App 20070011370 - Venkata; Ramanand ; et al.	2007-01-11
Voltage controlled oscillator programmable delay cells Grant 7,151,397 - Andrasic , et al. December 19, 2	2006-12-19
Programmable logic device multispeed I/O circuitry Grant 7,135,887 - Shumarayev , et al. November 14, 2	2006-11-14
Multiple data rates in programmable logic device serial interface App 20060233172 - Venkata; Ramanand ; et al.	2006-10-19
Methods and apparatus to DC couple LVDS driver to CML levels App 20060220681 - Wong; Wilson ; et al.	2006-10-05
Integrated circuit output driver circuitry with programmable preemphasis Grant 7,109,743 - Shumarayev , et al. September 19, 2	2006-09-19
Method and apparatus for multi-mode clock data recovery App 20060165204 - Shumarayev; Sergey Y. ; et al.	2006-07-27
Next generation 8B10B architecture App 20060095613 - Venkata; Ramanand ; et al.	2006-05-04
Integrated circuit output driver circuitry with programmable preemphasis App 20050237082 - Shumarayev, Sergey Y. ; et al.	2005-10-27
Integrated circuit output driver circuitry with programmable preemphasis Grant 6,940,302 - Shumarayev , et al. September 6, 2	2005-09-06
High-performance programmable logic architecture Grant 6,882,176 - Norman , et al. April 19, 2	2005-04-19
Voltage controlled oscillator programmable delay cells App 20050024158 - Andrasic, Stjepan William ; et al.	2005-02-03
Programmable logic device multispeed I/O circuitry Grant 6,831,480 - Shumarayev , et al. December 14, 2	2004-12-14
Nonvolatile memory cell with low doping region Grant 6,828,620 - Pass , et al. December 7, 2	2004-12-07
Voltage controlled oscillator programmable delay cells Grant 6,771,105 - Andrasic , et al. August 3, 2	2004-08-03
Programmable logic with lower internal voltage circuitry Grant 6,724,222 - Patel , et al. April 20, 2	2004-04-20
Nonvolatile memory cell with low doping region App 20030197218 - Pass, Christopher J. ; et al.	2003-10-23
Voltage controlled oscillator programmable delay cells App 20030155955 - Andrasic, Stjepan W. ; et al.	2003-08-21
Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions Grant 6,604,228 - Patel , et al. August 5, 2	2003-08-05
Programmable logic with lower internal voltage circuitry App 20030117174 - Patel, Rakesh H. ; et al.	2003-06-26
Overvoltage-tolerant interface for integrated circuits Grant 6,583,646 - Patel , et al. June 24, 2	2003-06-24
PLD with on-chip memory having a shadow register Grant 6,353,552 - Sample , et al. March 5, 2	2002-03-05
I/O buffer circuit with pin multiplexing Grant 6,285,211 - Sample , et al. September 4, 2	2001-09-04
Overvoltage-tolerant interface for intergrated circuits Grant 6,252,422 - Patel , et al. June 26, 2	2001-06-26
Sample and load scheme for observability internal nodes in a PLD Grant 6,243,304 - Patel , et al. June 5, 2	2001-06-05
Programmable logic device with multi-port memory Grant 6,219,284 - Sample , et al. April 17, 2	2001-04-17
Look-up table based logic element with complete permutability of the inputs to the secondary signals Grant 6,184,707 - Norman , et al. February 6, 2	2001-02-06
Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions Grant 6,175,952 - Patel , et al. January 16, 2	2001-01-16
Overvoltage-tolerant interface for integrated circuits Grant 6,147,511 - Patel , et al. November 14, 2	2000-11-14
Method of margin testing programmable interconnect cell Grant 6,122,209 - Pass , et al. September 19, 2	2000-09-19
Circuitry for a low internal voltage integrated circuit Grant 6,025,737 - Patel , et al. February 15, 2	2000-02-15
I/O buffer circuit with pin multiplexing Grant 6,020,760 - Sample , et al. February 1, 2	2000-02-01
Partially reconfigurable programmable logic device Grant 6,020,758 - Patel , et al. February 1, 2	2000-02-01
Sample and load scheme for observability of internal nodes in a PLD Grant 6,014,334 - Patel , et al. January 11, 2	2000-01-11
Programmable logic device with multi-port memory Grant 6,011,744 - Sample , et al. January 4, 2	2000-01-04
Programmable interconnect junction Grant 5,949,710 - Pass , et al. September 7, 1	1999-09-07
Programming programmable transistor devices using state machines Grant 5,869,980 - Chu , et al. February 9, 1	1999-02-09
Diagnostic interface system for programmable logic system development Grant 5,870,410 - Norman , et al. February 9, 1	1999-02-09
Method and apparatus for monitoring or forcing an internal node in a programmable device Grant 5,821,771 - Patel , et al. October 13, 1	1998-10-13
Look-up table based logic element with complete permutability of the inputs to the secondary signals Grant 5,821,773 - Norman , et al. October 13, 1	1998-10-13
Sample and load scheme for observability of internal nodes in a PLD Grant 5,764,079 - Patel , et al. June 9, 1	1998-06-09
Programming programmable transistor devices using state machines Grant 5,650,734 - Chu , et al. July 22, 1	1997-07-22
Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers Grant 5,483,178 - Costello , et al. January 9, 1	1996-01-09
Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements Grant 5,371,422 - Patel , et al. December 6, 1	1994-12-06
Programmable logic device with redundant circuitry Grant 5,369,314 - Patel , et al. November 29, 1	1994-11-29
Macrocell with flexible product term allocation Grant 5,350,954 - Patel September 27, 1	1994-09-27
I/O cell for programmable logic device providing latched, unlatched, and fast inputs Grant 5,317,210 - Patel May 31, 1	1994-05-31