Patel; Jyotica V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Patel; Jyotica V..The latest application filed is for "microfluidic chips with one or more vias filled with sacrificial plugs".

Company Profile

1.5.5

Patel; Jyotica V. - Port Chester NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Microfluidic chips with one or more vias filled with sacrificial plugs Grant 11,440,002 - Smith , et al. September 13, 2	2022-09-13
Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch Grant 10,714,341 - Cohen , et al.	2020-07-14
Microfluidic Chips With One Or More Vias Filled With Sacrificial Plugs App 20200122139 - Smith; Joshua T. ; et al.	2020-04-23
Reactive Ion Etching Assisted Lift-off Processes For Fabricating Thick Metallization Patterns With Tight Pitch App 20170243743 - Cohen; Guy M. ; et al.	2017-08-24
Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch Grant 9,728,444 - Cohen , et al. August 8, 2	2017-08-08
Reactive Ion Etching Assisted Lift-off Processes For Fabricating Thick Metallization Patterns With Tight Pitch App 20170194195 - Cohen; Guy M. ; et al.	2017-07-06
Mixed lithography with dual resist and a single pattern transfer Grant 8,334,090 - Fuller , et al. December 18, 2	2012-12-18
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20110123779 - Fuller; Nicholas C. ; et al.	2011-05-26
Mixed lithography with dual resist and a single pattern transfer Grant 7,914,970 - Fuller , et al. March 29, 2	2011-03-29
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20090092799 - Fuller; Nicholas C. ; et al.	2009-04-09

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