Pasternak; John
Patent Applications and Registrations
Patent applications and USPTO patent grants for Pasternak; John.The latest application filed is for "single phase clock-gating circuit".
- Pasternak; John - San Jose CA
- Pasternak; John - Santa Clara CA
- Pasternak; John - Fremont CA
| Patent | Date |
|---|---|
| Single phase clock-gating circuit Grant 11,159,163 - Jadhav , et al. October 26, 2 | 2021-10-26 |
| Single Phase Clock-gating Circuit App 20200395939 - Jadhav; Pradip Subhana ; et al. | 2020-12-17 |
| Multi-bit standard cells for consolidating transistors with selective sourcing Grant 9,432,003 - Pasternak August 30, 2 | 2016-08-30 |
| Multi-Bit Standard Cells For Consolidating Transistors With Selective Sourcing App 20150318845 - Pasternak; John | 2015-11-05 |
| Voltage regulator with bypass mode Grant 7,391,193 - Wang , et al. June 24, 2 | 2008-06-24 |
| Voltage regulator with bypass for multi-voltage storage system Grant 7,212,067 - Pasternak May 1, 2 | 2007-05-01 |
| Voltage regulator using protected low voltage devices Grant 7,164,561 - Wang , et al. January 16, 2 | 2007-01-16 |
| Voltage regulator with bypass mode App 20060164054 - Wang; Yongliang ; et al. | 2006-07-27 |
| Voltage regulator using protected low voltage devices App 20050179421 - Wang, Yongliang ; et al. | 2005-08-18 |
| Voltage regulator with bypass for multi-voltage storage system App 20050024128 - Pasternak, John | 2005-02-03 |
| Circuit for performing arithmetic operations Grant 5,394,450 - Pasternak February 28, 1 | 1995-02-28 |
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