loadpatents
name:-0.01599383354187
name:-0.013773918151855
name:-0.0003819465637207
Pastel; Leah M. Patent Filings

Pastel; Leah M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pastel; Leah M..The latest application filed is for "lateral silicon-on-insulator bipolar junction transistor process and structure".

Company Profile
0.15.15
  • Pastel; Leah M. - Essex Junction VT
  • Pastel; Leah M. - Essex VT
  • Pastel; Leah M. - Ossining NY
  • Pastel; Leah M. - Essex Highlands VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Lateral silicon-on-insulator bipolar junction transistor process and structure
Grant 9,397,203 - Colt, Jr. , et al. July 19, 2
2016-07-19
Data mining shape based data
Grant 9,244,946 - Kassab , et al. January 26, 2
2016-01-26
Data mining shape based data
Grant 9,235,601 - Kassab , et al. January 12, 2
2016-01-12
Lateral Silicon-on-insulator Bipolar Junction Transistor Process And Structure
App 20150214346 - Colt, JR.; John Z. ;   et al.
2015-07-30
Lateral silicon-on-insulator bipolar junction transistor process and structure
Grant 9,059,230 - Colt, Jr. , et al. June 16, 2
2015-06-16
Data Mining Shape Based Data
App 20140149458 - Kassab; Maroun M. ;   et al.
2014-05-29
Data Mining Shape Based Data
App 20140149408 - Kassab; Maroun M. ;   et al.
2014-05-29
Identifying defects
Grant 8,571,299 - Fayaz , et al. October 29, 2
2013-10-29
Insertion of faults in logic model used in simulation
Grant 8,566,059 - Desineni , et al. October 22, 2
2013-10-22
Identifying Defects
App 20120050728 - Fayaz; Mohammed F. ;   et al.
2012-03-01
Insertion Of Faults In Logic Model Used In Simulation
App 20110137602 - Desineni; Rao H. ;   et al.
2011-06-09
Scan chain diagnostics using logic paths
Grant 7,895,487 - Huisman , et al. February 22, 2
2011-02-22
Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning
Grant 7,895,545 - Cohn , et al. February 22, 2
2011-02-22
System and method for signature-based systematic condition detection and analysis
Grant 7,853,848 - Desineni , et al. December 14, 2
2010-12-14
Methods For Designing A Product Chip A Priori For Design Subsetting, Feature Analysis, And Yield Learning
App 20090259983 - Cohn; John M. ;   et al.
2009-10-15
System And Method For Signature-based Systematic Condition Detection And Analysis
App 20090106614 - Desineni; Rao H. ;   et al.
2009-04-23
Sensor differentiated fault isolation
Grant 7,397,263 - Condon , et al. July 8, 2
2008-07-08
Scan Chain Diagnostics Using Logic Paths
App 20070168805 - Huisman; Leendert M. ;   et al.
2007-07-19
Scan chain diagnostics using logic paths
Grant 7,240,261 - Huisman , et al. July 3, 2
2007-07-03
Inspection methods and structures for visualizing and/or detecting specific chip structures
Grant 7,230,335 - Cann , et al. June 12, 2
2007-06-12
Sensor Differentiated Fault Isolation
App 20070126450 - Condon; Kevin L. ;   et al.
2007-06-07
Sensor Differentiated Fault Isolation
App 20060232284 - Condon; Kevin L. ;   et al.
2006-10-19
Canary Device For Failure Analysis
App 20060195285 - Bouchard; Pierre J. ;   et al.
2006-08-31
Inspection Methods And Structures For Visualizing And/or Detecting Specific Chip Structures
App 20060071208 - Cann; Jerome L. ;   et al.
2006-04-06
Scan Chain Diagnostics Using Logic Paths
App 20050138508 - Huisman, Leendert M. ;   et al.
2005-06-23
Internal cache for on chip test data storage
Grant 6,901,542 - Bartenstein , et al. May 31, 2
2005-05-31
Internal cache for on chip test data storage
App 20030033566 - Bartenstein, Thomas W. ;   et al.
2003-02-13
Apparatus for assisting backside focused ion beam device modification
App 20030015671 - Lackey, David E. ;   et al.
2003-01-23

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