Pasdast; Gerald S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Pasdast; Gerald S..The latest application filed is for "shield structures in microelectronic assemblies having direct bonding".
- Pasdast; Gerald S. - San Jose CA
| Patent | Date |
|---|---|
| Shield Structures In Microelectronic Assemblies Having Direct Bonding App 20220199546 - Elsherbini; Adel A. ; et al. | 2022-06-23 |
| Semiconductor package or structure with dual-sided interposers and memory Grant 11,367,707 - Liff , et al. June 21, 2 | 2022-06-21 |
| Fast-lane routing for multi-chip packages Grant 11,336,559 - Elsherbini , et al. May 17, 2 | 2022-05-17 |
| Microelectronic Assemblies With Inductors In Direct Bonding Regions App 20220093547 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
| Capacitors And Resistors At Direct Bonding Interfaces In Microelectronic Assemblies App 20220093725 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
| Microelectronic Assemblies With Inductors In Direct Bonding Regions App 20220093546 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
| Phy-based Retry Techniques For Die-to-die Interfaces App 20210344354 - Lanka; Narasimha ; et al. | 2021-11-04 |
| Multichip package link Grant 11,003,610 - Wu , et al. May 11, 2 | 2021-05-11 |
| Approximate Data Bus Inversion Technique For Latency Sensitive Applications App 20210004347 - Lanka; Narasimha ; et al. | 2021-01-07 |
| Multichip Package Link App 20200320031 - Wu; Zuoguo ; et al. | 2020-10-08 |
| Semiconductor Package Or Semiconductor Package Structure With Dual-sided Interposer And Memory App 20200098725 - Liff; Shawna M. ; et al. | 2020-03-26 |
| Semiconductor Package Or Structure With Dual-sided Interposers And Memory App 20200098724 - Liff; Shawna M. ; et al. | 2020-03-26 |
| Serializer-deserializer Die For High Speed Signal Interconnect App 20200075521 - Elsherbini; Adel A. ; et al. | 2020-03-05 |
| Fast-lane Routing For Multi-chip Packages App 20200067816 - Elsherbini; Adel A. ; et al. | 2020-02-27 |
| Method, apparatus, system for centering in a high performance interconnect Grant 10,560,081 - Wagh , et al. Feb | 2020-02-11 |
| Multichip package link Grant 10,552,357 - Wu , et al. Fe | 2020-02-04 |
| Valid lane training Grant 10,461,805 - Iyer , et al. Oc | 2019-10-29 |
| Valid Lane Training App 20190238179 - Iyer; Venkatraman ; et al. | 2019-08-01 |
| Multichip Package Link App 20180300275 - Wu; Zuoguo J. ; et al. | 2018-10-18 |
| Multichip package link Grant 10,073,808 - Wu , et al. September 11, 2 | 2018-09-11 |
| Multichip package link Grant 9,946,676 - Wagh , et al. April 17, 2 | 2018-04-17 |
| Method, Apparatus, System For Centering In A High Performance Interconnect App 20170294906 - Wagh; Mahesh ; et al. | 2017-10-12 |
| Method, apparatus, system for centering in a high performance interconnect Grant 9,692,402 - Wagh , et al. June 27, 2 | 2017-06-27 |
| Multichip Package Link App 20170083475 - Wu; Zuoguo J. ; et al. | 2017-03-23 |
| Multichip Package Link App 20160283429 - Wagh; Mahesh ; et al. | 2016-09-29 |
| Method, Apparatus, System For Centering In A High Performance Interconnect App 20160191034 - Wagh; Mahesh ; et al. | 2016-06-30 |
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