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name:-0.026144027709961
name:-0.0085499286651611
name:-0.01031494140625
Pasdast; Gerald Patent Filings

Pasdast; Gerald

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pasdast; Gerald.The latest application filed is for "clock phase management for die-to-die (d2d) interconnect".

Company Profile
10.8.28
  • Pasdast; Gerald - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Clock Phase Management For Die-to-die (d2d) Interconnect
App 20220271912 - Pasdast; Gerald ;   et al.
2022-08-25
Valid Signal For Latency Sensitive Die-to-die (d2d) Interconnects
App 20220261308 - Lanka; Narasimha ;   et al.
2022-08-18
Clock-gating In Die-to-die (d2d) Interconnects
App 20220262756 - Lanka; Narasimha ;   et al.
2022-08-18
Link Initialization Training And Bring Up For Die-to-die Interconnect
App 20220237138 - Lanka; Narasimha ;   et al.
2022-07-28
Sideband Interface For Die-to-die Interconnects
App 20220222198 - Lanka; Narasimha ;   et al.
2022-07-14
Dual Loop Voltage Regulator
App 20220197321 - Tiagaraj; Sathya Narasimman ;   et al.
2022-06-23
Power-forwarding Bridge For Inter-chip Data Signal Transfer
App 20220199537 - Qian; Zhiguo ;   et al.
2022-06-23
Multiple dies hardware processors and methods
Grant 11,294,852 - Nassif , et al. April 5, 2
2022-04-05
Composite Interposer Structure And Method Of Providing Same
App 20220084949 - Elsherbini; Adel ;   et al.
2022-03-17
Composite interposer structure and method of providing same
Grant 11,270,947 - Elsherbini , et al. March 8, 2
2022-03-08
Multiple Dies Hardware Processors And Methods
App 20220050805 - NASSIF; NEVINE ;   et al.
2022-02-17
Vias In Composite Ic Chip Structures
App 20220037281 - Elsherbini; Adel ;   et al.
2022-02-03
Scalable And Interoperable Phyless Die-to-die Io Solution
App 20210398906 - QIAN; Zhiguo ;   et al.
2021-12-23
Vias in composite IC chip structures
Grant 11,205,630 - Elsherbini , et al. December 21, 2
2021-12-21
Composite Ic Chips Including A Chiplet Embedded Within Metallization Layers Of A Host Ic Chip
App 20210375830 - Elsherbini; Adel ;   et al.
2021-12-02
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
Grant 11,094,672 - Elsherbini , et al. August 17, 2
2021-08-17
Skip Level Vias In Metallization Layers For Integrated Circuit Devices
App 20210202377 - Elsherbini; Adel ;   et al.
2021-07-01
Composite Interposer Structure And Method Of Providing Same
App 20210159179 - Elsherbini; Adel ;   et al.
2021-05-27
Packaged device with a chiplet comprising memory resources
Grant 10,998,302 - Elsherbini , et al. May 4, 2
2021-05-04
Composite Ic Chips Including A Chiplet Embedded Within Metallization Layers Of A Host Ic Chip
App 20210098422 - Elsherbini; Adel ;   et al.
2021-04-01
Vias In Composite Ic Chip Structures
App 20210098407 - Elsherbini; Adel ;   et al.
2021-04-01
Packaged Device With A Chiplet Comprising Memory Resources
App 20210098440 - Elsherbini; Adel ;   et al.
2021-04-01
Inter-die passive interconnects approaching monolithic performance
Grant 10,854,548 - Wu , et al. December 1, 2
2020-12-01
Multiple Dies Hardware Processors And Methods
App 20200334196 - NASSIF; NEVINE ;   et al.
2020-10-22
Multiple dies hardware processors and methods
Grant 10,795,853 - Nassif , et al. October 6, 2
2020-10-06
Inter-die Passive Interconnects Approaching Monolithic Performance
App 20200211965 - Wu; Zuoguo ;   et al.
2020-07-02
Clock phase compensation apparatus and method
Grant 10,686,582 - Pasdast , et al.
2020-06-16
Single Clock Source For A Multiple Die Package
App 20190041895 - Miao; Yingyu ;   et al.
2019-02-07
Multiple Dies Hardware Processors And Methods
App 20180101502 - NASSIF; NEVINE ;   et al.
2018-04-12

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