Parveen; Nasima
Patent Applications and Registrations
Patent applications and USPTO patent grants for Parveen; Nasima.The latest application filed is for "proactive di/dt voltage droop mitigation".
- Parveen; Nasima - San Jose CA
| Patent | Date |
|---|---|
| Proactive Di/Dt voltage droop mitigation Grant 11,204,766 - Kim , et al. December 21, 2 | 2021-12-21 |
| Proactive Di/dt Voltage Droop Mitigation App 20190384603 - Kim; Jason Seung-Min ; et al. | 2019-12-19 |
| Dual mode AES implementation to support single and multiple AES operations Grant 7,769,166 - Parveen , et al. August 3, 2 | 2010-08-03 |
| Low jitter and/or fast lock-in clock recovery circuit Grant 7,545,900 - Leung , et al. June 9, 2 | 2009-06-09 |
| Dual mode AES implementation to support single and multiple AES operations App 20080069339 - Parveen; Nasima ; et al. | 2008-03-20 |
| Low jitter and/or fast lock-in clock recovery circuit App 20070110206 - Leung; Ho-Ming ; et al. | 2007-05-17 |
| Quotient digit selection logic for floating point division/square root Grant 5,954,789 - Yu , et al. September 21, 1 | 1999-09-21 |
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