Partovi; Hamid
Patent Applications and Registrations
Patent applications and USPTO patent grants for Partovi; Hamid.The latest application filed is for "techniques for statistical frequency enhancement of statically timed designs".
Company Profile
3.39.14
- Partovi; Hamid - Menlo Park CA
- Partovi; Hamid - Los Altos CA
- - Los Altos CA US
- Partovi; Hamid - Sunnyvale CA
- Partovi; Hamid - San Jose CA
- Partovi; Hamid - Mountain View CA
- Partovi; Hamid - Westboro MA
- Partovi; Hamid - Westborough MA
Patent Activity
| Patent | Date |
|---|---|
| Techniques for statistical frequency enhancement of statically timed designs Grant 10,318,676 - Yeung , et al. | 2019-06-11 |
| Variation immune on-die voltage droop detector Grant 10,162,373 - Chong , et al. Dec | 2018-12-25 |
| Self-referenced on-die voltage droop detector Grant 10,145,868 - Chong , et al. De | 2018-12-04 |
| Techniques For Statistical Frequency Enhancement Of Statically Timed Designs App 20180210987 - Yeung; Alfred ; et al. | 2018-07-26 |
| Self-referenced On-die Voltage Droop Detector App 20170261537 - Chong; Yan ; et al. | 2017-09-14 |
| High frequency voltage supply monitor Grant 9,568,511 - Ravezzi , et al. February 14, 2 | 2017-02-14 |
| High Frequency Voltage Supply Monitor App 20150323569 - Ravezzi; Luca ; et al. | 2015-11-12 |
| Shadow latch Grant 8,618,856 - Yeung , et al. December 31, 2 | 2013-12-31 |
| Shadow latch Grant 08618856 - | 2013-12-31 |
| Pseudo single-phase flip-flop (PSP-FF) Grant 8,604,854 - Partovi , et al. December 10, 2 | 2013-12-10 |
| Pass gate shadow latch Grant 8,497,721 - Partovi , et al. July 30, 2 | 2013-07-30 |
| Hazard-free minimal-latency flip-flop (HFML-FF) Grant 8,421,514 - Yeung , et al. April 16, 2 | 2013-04-16 |
| Digital CMOS circuit with noise cancellation Grant 8,384,421 - Ravezzi , et al. February 26, 2 | 2013-02-26 |
| Integrated circuit including calibration circuit Grant 7,991,573 - Homer , et al. August 2, 2 | 2011-08-02 |
| Wide-band Low-voltage IQ-generating Ring-oscillator-based CMOS VCO App 20110012685 - Partovi; Hamid ; et al. | 2011-01-20 |
| Electrical idle detection circuit including input signal rectifier Grant 7,813,289 - Partovi , et al. October 12, 2 | 2010-10-12 |
| Data sampler including a first stage and a second stage Grant 7,733,815 - Gopalakrishnan , et al. June 8, 2 | 2010-06-08 |
| Clock data recovery circuit with circuit loop disablement Grant 7,681,063 - Partovi , et al. March 16, 2 | 2010-03-16 |
| Integrated Circuit With Reduced Pointer Uncertainly App 20090180335 - Chokkalingam; Sivaraman ; et al. | 2009-07-16 |
| Integrated Circuit Including Impedance To Provide Symmetrical Differential Signals App 20090160559 - Ravezzi; Luca ; et al. | 2009-06-25 |
| Integrated Circuit Including Calibration Circuit App 20090164165 - Homer; Russell ; et al. | 2009-06-25 |
| CDR-based clock synthesis Grant 7,480,358 - Partovi , et al. January 20, 2 | 2009-01-20 |
| Data sampler including a first stage and a second stage App 20080024215 - Gopalakrishnan; Karthik ; et al. | 2008-01-31 |
| Signal converter circuit App 20070252618 - Gopalakrishnan; Karthik ; et al. | 2007-11-01 |
| Operational amplifier App 20070252648 - Ravezzi; Luca ; et al. | 2007-11-01 |
| Electrical idle detection circuit including input signal rectifier App 20070180281 - Partovi; Hamid ; et al. | 2007-08-02 |
| Clock data recovery circuit with circuit loop disablement App 20060227914 - Partovi; Hamid ; et al. | 2006-10-12 |
| Amplitude control circuit Grant 7,061,337 - Partovi , et al. June 13, 2 | 2006-06-13 |
| Amplitude control circuit App 20060012447 - Partovi; Hamid ; et al. | 2006-01-19 |
| CDR-based clock synthesis App 20050193301 - Partovi, Hamid ; et al. | 2005-09-01 |
| Interconnect methodology employing a low dielectric constant etch stop layer Grant 6,593,632 - Avanzino , et al. July 15, 2 | 2003-07-15 |
| Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer Grant 6,137,126 - Avanzino , et al. October 24, 2 | 2000-10-24 |
| Dynamic NOR gates for NAND decode Grant 6,081,136 - Khanna , et al. June 27, 2 | 2000-06-27 |
| Latching method Grant 5,990,717 - Partovi , et al. November 23, 1 | 1999-11-23 |
| Self-timed pulse control circuit Grant 5,964,884 - Partovi , et al. October 12, 1 | 1999-10-12 |
| Phase frequency detector having reduced blind spot Grant 5,963,059 - Partovi , et al. October 5, 1 | 1999-10-05 |
| Dynamic latching device Grant 5,764,089 - Partovi , et al. June 9, 1 | 1998-06-09 |
| Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps Grant 5,617,283 - Krakauer , et al. April 1, 1 | 1997-04-01 |
| Output buffer with improved tolerance to overvoltage Grant 5,576,635 - Partovi , et al. November 19, 1 | 1996-11-19 |
| Static random access memory having tunable-self-timed control logic circuits Grant 5,546,354 - Partovi , et al. August 13, 1 | 1996-08-13 |
| Method and apparatus using mapped redundancy to perform multiple large block memory array repair Grant 5,495,447 - Butler , et al. February 27, 1 | 1996-02-27 |
| Carry chain adder using regenerative push-pull differential logic Grant 5,487,025 - Partovi , et al. January 23, 1 | 1996-01-23 |
| Noise-free analog islands in digital integrated circuits Grant 5,453,713 - Partovi , et al. September 26, 1 | 1995-09-26 |
| Voltage level converting buffer circuit Grant 5,378,945 - Partovi , et al. January 3, 1 | 1995-01-03 |
| Fast tag compare and bank select in set associative cache Grant 5,353,424 - Partovi , et al. October 4, 1 | 1994-10-04 |
| Resistance tester utilizing regulator circuits Grant 5,272,445 - Lloyd , et al. December 21, 1 | 1993-12-21 |
| Subarray architecture with partial address translation Grant 5,253,203 - Partovi , et al. October 12, 1 | 1993-10-12 |
| Noise reduction in CMOS driver using capacitor discharge to generate a control voltage Grant 4,972,101 - Partovi , et al. November 20, 1 | 1990-11-20 |
| Output buffer arrangement for reducing chip noise without speed penalty Grant 4,857,770 - Partovi , et al. August 15, 1 | 1989-08-15 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 