Parris; Michael Curtis

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parris; Michael Curtis.The latest application filed is for "system and method for testing fuse blow reliability for integrated circuits".

Company Profile

0.9.10

Parris; Michael Curtis - San Jose CA
Parris, Michael Curtis - Colorado Springs CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for testing fuse blow reliability for integrated circuits Grant 9,557,364 - Parris January 31, 2	2017-01-31
Non-volatile memory devices having vertical drain to gate capacitive coupling Grant 9,230,814 - Fisch , et al. January 5, 2	2016-01-05
Embedded passive integration Grant 8,970,003 - Parris March 3, 2	2015-03-03
Common doped region with separate gate control for a logic compatible non-volatile memory cell Grant 8,873,302 - Fisch , et al. October 28, 2	2014-10-28
System And Method For Testing Fuse Blow Reliability For Integrated Circuits App 20140253145 - Parris; Michael Curtis	2014-09-11
System and method for testing fuse blow reliability for integrated circuits Grant 8,736,278 - Parris May 27, 2	2014-05-27
Non-volatile Memory Devices Having Vertical Drain To Gate Capacitive Coupling App 20130107630 - Fisch; David Edward ; et al.	2013-05-02
Common Doped Region With Separate Gate Control For A Logic Compatible Non-volatile Memory Cell App 20130107635 - Fisch; David Edward ; et al.	2013-05-02
System And Method For Testing Fuse Blow Reliability For Integrated Circuits App 20130027056 - Parris; Michael Curtis	2013-01-31
Embedded Passive Integration App 20130027899 - Parris; Michael Curtis	2013-01-31
Small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays App 20020136051 - Hardee, Kim Carver ; et al.	2002-09-26

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