Parris; Michael C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parris; Michael C..The latest application filed is for "dram security erase".

Company Profile

0.47.40

Parris; Michael C. - Colorado Springs CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
DRAM security erase Grant 9,558,808 - Parris January 31, 2	2017-01-31
DRAM security erase App 20160211009 - PARRIS; Michael C.	2016-07-21
DRAM security erase Grant 9,299,417 - Parris March 29, 2	2016-03-29
Dram Security Erase App 20150287452 - Parris; Michael C.	2015-10-08
DRAM security erase Grant 8,976,572 - Parris March 10, 2	2015-03-10
Power Boosting Circuit For Semiconductor Packaging App 20140333371 - Crisp; Richard Dewitt ; et al.	2014-11-13
Dram Security Erase App 20140185402 - Parris; Michael C.	2014-07-03
DRAM security erase Grant 8,699,263 - Parris April 15, 2	2014-04-15
Power boosting circuit for semiconductor packaging Grant 8,692,611 - Crisp , et al. April 8, 2	2014-04-08
Data inversion register technique for integrated circuit memory testing Grant RE44,726 - Parris , et al. January 21, 2	2014-01-21
Dram Security Erase App 20130051127 - Parris; Michael C.	2013-02-28
Power Boosting Circuit For Semiconductor Packaging App 20130043935 - Crisp; Richard Dewitt ; et al.	2013-02-21
Dual bit line precharge architecture and method for low power dynamic random access memory (DRAM) integrated circuit devices and devices incorporating embedded DRAM Grant 8,339,882 - Parris , et al. December 25, 2	2012-12-25
Error correction code (ECC) circuit test mode Grant 8,281,219 - Parris , et al. October 2, 2	2012-10-02
Dual Bit Line Precharge Architecture And Method For Low Power Dynamic Random Access Memory (dram) Integrated Circuit Devices And Devices Incorporating Embedded Dram App 20120008444 - Parris; Michael C. ; et al.	2012-01-12
Dual Bit Line Precharge Architecture And Method For Low Power Dynamic Random Access Memory (dram) Integrated Circuit Devices And Devices Incorporating Embedded Dram App 20120008445 - Parris; Michael C. ; et al.	2012-01-12
Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM Grant 7,916,567 - Parris , et al. March 29, 2	2011-03-29
Short-circuit charge-sharing technique for integrated circuit devices Grant 7,649,406 - Parris , et al. January 19, 2	2010-01-19
Data inversion register technique for integrated circuit memory testing Grant 7,631,233 - Parris , et al. December 8, 2	2009-12-08
Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values Grant 7,609,570 - Parris , et al. October 27, 2	2009-10-27
Optimized charge sharing for data bus skew applications Grant 7,606,093 - Parris , et al. October 20, 2	2009-10-20
Twin Cell Architecture For Integrated Circuit Dynamic Random Access Memory (dram) Devices And Those Devices Incorporating Embedded Dram App 20090225613 - Parris; Michael C. ; et al.	2009-09-10
Low skew clock distribution tree Grant 7,586,355 - Parris , et al. September 8, 2	2009-09-08
Multiple bus charge sharing Grant 7,580,304 - Parris August 25, 2	2009-08-25
Static Random Access Memory (sram) Compatible, High Availability Memory Array And Method Employing Synchronous Dynamic Random Access Memory (dram) In Conjunction With A Data Cache And Separate Read And Write Registers And Tag Blocks App 20090106488 - Butler; Douglas Blaine ; et al.	2009-04-23
Data Inversion Register Technique For Integrated Circuit Memory Testing App 20090094497 - Parris; Michael C. ; et al.	2009-04-09
Short-circuit Charge-sharing Technique For Integrated Circuit Devices App 20090072879 - Parris; Michael C. ; et al.	2009-03-19
Early Write With Data Masking Technique For Integrated Circuit Dynamic Random Access Memory (dram) Devices And Those Incorporating Embedded Dram App 20090073786 - Parris; Michael C. ; et al.	2009-03-19
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks Grant 7,506,100 - Butler , et al. March 17, 2	2009-03-17
Error Correction Code (ecc) Circuit Test Mode App 20090049350 - Parris; Michael C. ; et al.	2009-02-19
Low Skew Clock Distribution Tree App 20090015311 - Parris; Michael C. ; et al.	2009-01-15
Multiple Bus Charge Sharing App 20080313379 - Parris; Michael C.	2008-12-18
Data bus charge-sharing technique for integrated circuit devices Grant 7,463,054 - Parris , et al. December 9, 2	2008-12-09
Optimized Charge Sharing For Data Bus Skew Applications App 20080174340 - Parris; Michael C. ; et al.	2008-07-24
Switched Capacitor Charge Sharing Technique For Integrated Circuit Devices Enabling Signal Generation Of Disparate Selected Signal Values App 20080175074 - Parris; Michael C. ; et al.	2008-07-24
Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices Grant 7,298,171 - Parris November 20, 2	2007-11-20
Powergating method and apparatus Grant 7,180,363 - Parris , et al. February 20, 2	2007-02-20
Layout area efficient, high speed, dynamic multi-input exclusive or (XOR) and exclusive NOR (XNOR) logic gate circuit designs for integrated circuit devices App 20070008014 - Parris; Michael C.	2007-01-11
Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays Grant 7,161,214 - Parris January 9, 2	2007-01-09
Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM Grant 7,154,795 - Parris , et al. December 26, 2	2006-12-26
Dual access DRAM Grant 7,110,306 - Parris , et al. September 19, 2	2006-09-19
Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM Grant 7,099,234 - Parris , et al. August 29, 2	2006-08-29
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag App 20060190678 - Butler; Douglas Blaine ; et al.	2006-08-24
Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks App 20060190676 - Butler; Douglas Blaine ; et al.	2006-08-24
Powergate control using boosted and negative voltages Grant 7,053,692 - Parris , et al. May 30, 2	2006-05-30
Dual word line mode for DRAMs Grant 7,002,874 - Parris , et al. February 21, 2	2006-02-21
Powergating method and apparatus App 20060022742 - Parris; Michael C. ; et al.	2006-02-02
Clock signal initiated precharge technique for active memory subarrays in dynamic random access memory (DRAM) devices and other integrated circuit devices incorporating embedded DRAM App 20060023530 - Parris; Michael C. ; et al.	2006-02-02
Cache and tag power-down function during low-power data retention standby mode technique for cached integrated circuit memory devices App 20060005053 - Jones; Oscar Frederick JR. ; et al.	2006-01-05
Dual-port DRAM cell with simultaneous access App 20050289293 - Parris, Michael C. ; et al.	2005-12-29
Dual access DRAM App 20050286291 - Parris, Michael C. ; et al.	2005-12-29
Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM App 20050286339 - Parris, Michael C. ; et al.	2005-12-29
Non-contiguous masked refresh for an integrated circuit memory Grant 6,912,168 - Parris , et al. June 28, 2	2005-06-28
Non-contiguous masked refresh for an integrated circuit memory App 20040184334 - Parris, Michael C. ; et al.	2004-09-23
Bitline reference voltage circuit Grant 6,788,590 - Parris , et al. September 7, 2	2004-09-07
Bitline Reference Voltage Circuit App 20040141360 - Parris, Michael C. ; et al.	2004-07-22
Reduced gate delay multiplexed interface and output buffer circuit for integrated circuit devices incorporating random access memory arrays App 20040141401 - Parris, Michael C.	2004-07-22
Powergate control using boosted and negative voltages App 20040119529 - Parris, Michael C. ; et al.	2004-06-24
Asynchronous input data path technique for increasing speed and reducing latency in integrated circuit devices incorporating dynamic random access memory (DRAM) arrays and embedded DRAM Grant 6,744,690 - Parris June 1, 2	2004-06-01
Optimized read data amplifier and method for operating the same in conjunction with integrated circuit devices incorporating memory arrays Grant 6,738,302 - Parris , et al. May 18, 2	2004-05-18
Asynchronous Input Data Path Technique For Increasing Speed And Reducing Latency In Integrated Circuit Devices Incorporating Dynamic Random Access Memory (dram) Arrays And Embedded Dram App 20040090855 - Parris, Michael C.	2004-05-13
High voltage transistor protection technique and switching circuit for integrated circuit devices utilizing multiple power supply voltages Grant 6,731,156 - Parris , et al. May 4, 2	2004-05-04
Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry Grant 6,732,305 - Jones, Jr. , et al. May 4, 2	2004-05-04
Time data compression technique for high speed integrated circuit memory devices Grant 6,728,931 - Parris , et al. April 27, 2	2004-04-27
System and method for high speed integrated circuit device testing utilizing a lower speed test environment Grant 6,657,461 - Jones, Jr. , et al. December 2, 2	2003-12-02
Simultaneous function dynamic random access memory device technique Grant 6,643,212 - Jones, Jr. , et al. November 4, 2	2003-11-04
Simultaneous Function Dynamic Random Access Memory Device Technique App 20030198119 - Jones, Oscar Frederick JR. ; et al.	2003-10-23
Data path decoding technique for an embedded memory array Grant 6,625,069 - Parris , et al. September 23, 2	2003-09-23
Data path decoding technique for an embedded memory array Grant 6,625,066 - Parris , et al. September 23, 2	2003-09-23
Data Path Decoding Technique For An Embedded Memory Array App 20030174542 - Parris, Michael C. ; et al.	2003-09-18
Data Path Decoding Technique For An Embedded Memory Array App 20030174546 - Parris, Michael C. ; et al.	2003-09-18
Automatic delay technique for early read and write operations in synchronous dynamic random access memories Grant 6,608,797 - Parris , et al. August 19, 2	2003-08-19
Dynamic predecoder circuitry for memory circuits Grant 6,597,201 - Parris , et al. July 22, 2	2003-07-22
Shared sense amplifier driver technique for dynamic random access memories exhibiting improved write recovery time Grant 6,515,926 - Parris , et al. February 4, 2	2003-02-04
Technique for efficient logic power gating with data retention in integrated circuit devices Grant 6,512,394 - Parris January 28, 2	2003-01-28
Time data compression technique for high speed integrated circuit memory devices App 20020178413 - Parris, Michael C. ; et al.	2002-11-28
System and method for high speed integrated circuit device testing utilizing a lower speed test environment App 20020135393 - Jones, Oscar Frederick JR. ; et al.	2002-09-26
Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry App 20020042898 - Jones, Oscar Frederick JR. ; et al.	2002-04-11
Self-timed data amplifier and method for an integrated circuit memory device Grant 6,160,743 - Parris December 12, 2	2000-12-12
Circuit and method for accessing memory cells of a memory device Grant 5,680,362 - Parris , et al. October 21, 1	1997-10-21
DRAM having self-timed burst refresh mode Grant 5,430,680 - Parris July 4, 1	1995-07-04
DRAM variable row select Grant 5,331,601 - Parris July 19, 1	1994-07-19