Parrillo; Louis C.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Parrillo; Louis C..The latest application filed is for "vertical cross-point memory arrays".
- Parrillo; Louis C. - Austin TX
- Parrillo; Louis C. - Warren NJ
| Patent | Date |
|---|---|
| Vertical Cross-point Memory Arrays App 20200258940 - A1 | 2020-08-13 |
| Vertical cross-point memory arrays Grant 10,529,778 - Vereen , et al. J | 2020-01-07 |
| Systems and methods for a frame hanging device Grant 10,448,763 - Parrillo Oc | 2019-10-22 |
| Vertical Cross-point Memory Arrays App 20190051701 - Vereen; Lidia ; et al. | 2019-02-14 |
| Vertical cross-point memory arrays Grant 10,050,086 - Vereen , et al. August 14, 2 | 2018-08-14 |
| Systems And Methods For A Frame Hanging Device App 20170095094 - PARRILLO; LOUIS C. | 2017-04-06 |
| Vertical Cross-point Memory Arrays App 20170033158 - Vereen; Lidia ; et al. | 2017-02-02 |
| Systems and methods for a frame hanging device Grant 9,549,624 - Parrillo January 24, 2 | 2017-01-24 |
| Systems And Methods For A Frame Hanging Device App 20160081496 - PARRILLO; LOUIS C. | 2016-03-24 |
| Process for fabricating a semiconductor device having an improved metal interconnect structure Grant 5,527,739 - Parrillo , et al. June 18, 1 | 1996-06-18 |
| Semiconductor device having an improved metal interconnect structure Grant 5,442,235 - Parrillo , et al. August 15, 1 | 1995-08-15 |
| Wireless motor vehicle diagnostic and software upgrade system Grant 5,442,553 - Parrillo August 15, 1 | 1995-08-15 |
| Hot electron collector for a LDD transistor Grant 4,951,100 - Parrillo August 21, 1 | 1990-08-21 |
| High/low doping profile for twin well process Grant 4,929,565 - Parrillo May 29, 1 | 1990-05-29 |
| High/low doping profile for twin well process Grant 4,889,825 - Parrillo December 26, 1 | 1989-12-26 |
| Micron and submicron patterning without using a lithographic mask having submicron dimensions Grant 4,812,418 - Pfiester , et al. March 14, 1 | 1989-03-14 |
| Multiple step formation of conductive material layers Grant 4,808,555 - Mauntel , et al. February 28, 1 | 1989-02-28 |
| Methods for fabricating latchup-preventing CMOS device Grant 4,766,090 - Coquin , et al. August 23, 1 | 1988-08-23 |
| Method for preventing latchup in CMOS devices Grant 4,762,802 - Parrillo August 9, 1 | 1988-08-09 |
| LDD CMOS process Grant 4,753,898 - Parrillo , et al. June 28, 1 | 1988-06-28 |
| Removable sidewall spacer for lightly doped drain formation using one mask level and differential oxidation Grant 4,745,086 - Parrillo , et al. May 17, 1 | 1988-05-17 |
| Removable sidewall spacer for lightly doped drain formation using two mask levels Grant 4,722,909 - Parrillo , et al. February 2, 1 | 1988-02-02 |
| CMOS process Grant 4,717,683 - Parrillo , et al. January 5, 1 | 1988-01-05 |
| Integrated circuit trench cell Grant 4,686,552 - Teng , et al. August 11, 1 | 1987-08-11 |
| Latchup-preventing CMOS device Grant 4,647,957 - Coquin , et al. March 3, 1 | 1987-03-03 |
| Latchup-preventing CMOS device Grant 4,646,123 - Lynch , et al. February 24, 1 | 1987-02-24 |
| Nitrided silicon dioxide layers for semiconductor integrated circuits Grant 4,623,912 - Chang , et al. November 18, 1 | 1986-11-18 |
| Ethylene glycol etch for processes using metal silicides Grant 4,569,722 - Maury , et al. February 11, 1 | 1986-02-11 |
| CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well Grant 4,554,726 - Hillenius , et al. November 26, 1 | 1985-11-26 |
| Process for forming complementary integrated circuit devices Grant 4,435,895 - Parrillo , et al. March 13, 1 | 1984-03-13 |
| Method for fabricating complementary field effect transistor devices Grant 4,435,896 - Parrillo , et al. March 13, 1 | 1984-03-13 |
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