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name:-0.015262126922607
name:-0.011565208435059
name:-0.0046181678771973
Parker; Rachael J. Patent Filings

Parker; Rachael J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parker; Rachael J..The latest application filed is for "method, system and apparatus for error correction coding embedded in physically unclonable function arrays".

Company Profile
4.10.13
  • Parker; Rachael J. - Forest Grove OR
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method, System and Apparatus for Error Correction Coding Embedded in Physically Unclonable Function Arrays
App 20220253525 - Shen; Kuan-Yueh ;   et al.
2022-08-11
Method, system and apparatus for error correction coding embedded in physically unclonable function arrays
Grant 11,321,459 - Shen , et al. May 3, 2
2022-05-03
Random number generator including entropy source
Grant 10,656,916 - Parker , et al.
2020-05-19
Random Number Generator Including Entropy Source
App 20190205098 - Parker; Rachael J. ;   et al.
2019-07-04
Method, System and Apparatus for Error Correction Coding Embedded in Physically Unclonable Function Arrays
App 20190130103 - Shen; Kuan-Yueh ;   et al.
2019-05-02
Random number generator including entropy source
Grant 10,168,994 - Parker , et al. J
2019-01-01
Random Number Generator Including Entropy Source
App 20180293053 - Parker; Rachael J. ;   et al.
2018-10-11
Hardware-embedded key based on random variations of a stress-hardened inegrated circuit
Grant 9,391,617 - Mathew , et al. July 12, 2
2016-07-12
Secret operations using reconfigurable logics
Grant 9,264,048 - Parker February 16, 2
2016-02-16
Secret Operations Using Reconfigurable Logics
App 20150171870 - Parker; Rachael J.
2015-06-18
Hardware-embedded Key Based On Random Variations Of A Stress-hardened Inegrated Circuit
App 20140266297 - Mathew; Sanu K. ;   et al.
2014-09-18
Method and apparatus for independent control of devices under test connected in parallel
Grant 7,231,552 - Parker , et al. June 12, 2
2007-06-12
Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains
Grant 7,157,950 - Law , et al. January 2, 2
2007-01-02
Power-on detect circuit for use with multiple voltage domains
Grant 7,049,865 - Parker , et al. May 23, 2
2006-05-23
Methods and apparatuses for detecting clock loss in a phase-locked loop
Grant 7,038,508 - Parker , et al. May 2, 2
2006-05-02
Methods and apparatuses for detecting clock loss in a phase-locked loop
App 20050242852 - Parker, Rachael J. ;   et al.
2005-11-03
Fuse sense circuit
App 20050200385 - Parker, Rachael J. ;   et al.
2005-09-15
Power-on detect circuit for use with multiple voltage domains
App 20050195000 - Parker, Rachael J. ;   et al.
2005-09-08
Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains
App 20040260963 - Law, Hon-Mo Raymond ;   et al.
2004-12-23
Method and apparatus for independent control of devices under test connected in parallel
App 20040083414 - Parker, Rachael J. ;   et al.
2004-04-29

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