Parker; Donald D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parker; Donald D..The latest application filed is for "response and data phases in a highly pipelined bus architecture".

Company Profile

0.14.5

Parker; Donald D. - Beaverton OR
Parker; Donald D. - Portland OR
Parker; Donald D. - Orem UT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Enhanced highly pipelined bus architecture Grant 6,907,487 - Singh , et al. June 14, 2	2005-06-14
Snoop phase in a highly pipelined bus architecture Grant 6,880,031 - Singh , et al. April 12, 2	2005-04-12
Quad pumped bus architecture and protocol Grant 6,807,592 - Singh , et al. October 19, 2	2004-10-19
Response and data phases in a highly pipelined bus architecture Grant 6,804,735 - Singh , et al. October 12, 2	2004-10-12
Quad pumped bus architecture and protocol Grant 6,609,171 - Singh , et al. August 19, 2	2003-08-19
Quad pumped bus architecture and protocol Grant 6,601,121 - Singh , et al. July 29, 2	2003-07-29
Response and data phases in a highly pipelined bus architecture App 20020147875 - Singh, Gurbir ; et al.	2002-10-10
Quad pumped bus architecture and protocol App 20020038397 - Singh, Gurbir ; et al.	2002-03-28
Quad pumped bus architecture and protocol App 20020029307 - Singh, Gurbir ; et al.	2002-03-07
Enhanced highly pipelined bus architecture App 20010037421 - Singh, Gurbir ; et al.	2001-11-01
Snoop phase in a highly pipelined bus architecture App 20010037424 - Singh, Gurbir ; et al.	2001-11-01
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer Grant 5,822,555 - Brown , et al. October 13, 1	1998-10-13
Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue Grant 5,673,427 - Brown , et al. September 30, 1	1997-09-30
Decoder for decoding multiple instructions in parallel Grant 5,630,083 - Carbine , et al. May 13, 1	1997-05-13
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer Grant 5,600,806 - Brown , et al. February 4, 1	1997-02-04
Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders Grant 5,586,277 - Brown , et al. December 17, 1	1996-12-17
Decoding circuit and method providing immediate data for a micro-operation issued from a decoder Grant 5,581,717 - Boggs , et al. December 3, 1	1996-12-03
Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation Grant 5,559,974 - Boggs , et al. September 24, 1	1996-09-24
Livestock detaining gate Grant 4,302,908 - Parker December 1, 1	1981-12-01

Company Registrations

SEC

0001231696

PARKER DONALD D

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