Park; Sheung-Hee

Patent Applications and Registrations

Patent applications and USPTO patent grants for Park; Sheung-Hee.The latest application filed is for "selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory".

Company Profile

0.14.6

Park; Sheung-Hee - Pleasanton CA
Park; Sheung Hee - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory Grant 7,952,938 - Kathawala , et al. May 31, 2	2011-05-31
Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory App 20100208527 - Kathawala; Gulzar Ahmed ; et al.	2010-08-19
Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory Grant 7,746,705 - Ahmed Kathawala , et al. June 29, 2	2010-06-29
Flash memory device having increased over-erase correction efficiency and robustness against device variations Grant 7,599,228 - Lu , et al. October 6, 2	2009-10-06
Cycling improvement using higher erase bias Grant 7,561,471 - Park , et al. July 14, 2	2009-07-14
Selective Application Of Word Line Bias To Minimize Fringe Effects In Electromagnetic Fields During Erase Of Nonvolatile Memory App 20090147589 - Kathawala; Gulzar Ahmed ; et al.	2009-06-11
Repetitive Erase Verify Technique For Flash Memory Devices App 20080151636 - Park; Sheung-Hee ; et al.	2008-06-26
Cycling improvement using higher erase bias App 20080151644 - Park; Sheung-Hee ; et al.	2008-06-26
Repetitive erase verify technique for flash memory devices Grant 7,385,851 - Park , et al. June 10, 2	2008-06-10
Ramp Gate Erase For Dual Bit Flash Memory App 20080037330 - Park; Sheung-Hee ; et al.	2008-02-14
Ramp gate erase for dual bit flash memory Grant 7,319,615 - Park , et al. January 15, 2	2008-01-15
Flash memory with buried bit lines Grant 7,288,809 - Fastow , et al. October 30, 2	2007-10-30
Positive gate stress during erase to improve retention in multi-level, non-volatile flash memory Grant 7,142,455 - Lee , et al. November 28, 2	2006-11-28
Ramped soft programming for control of erase voltage distributions in flash memory devices Grant 7,020,021 - Leung , et al. March 28, 2	2006-03-28
Reading flash memory Grant 6,950,344 - Fastow , et al. September 27, 2	2005-09-27
Programming of a flash memory cell Grant 6,937,518 - Park , et al. August 30, 2	2005-08-30
Flash memory cell having reduced leakage current Grant 6,897,518 - Park , et al. May 24, 2	2005-05-24
Method of programming a memory cell Grant 6,781,885 - Park , et al. August 24, 2	2004-08-24
Method of programming memory cells Grant 6,754,109 - Fastow , et al. June 22, 2	2004-06-22
Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell App 20020106852 - He, Yue-Song ; et al.	2002-08-08

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