Park; Jonathan C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Park; Jonathan C..The latest application filed is for "gate array architecture with multiple programmable regions".

Company Profile

0.9.4

Park; Jonathan C. - Morgan Hill CA
Park; Jonathan C - San Jose CA
Park; Jonathan C. - San Jose CA
Park; Jonathan C. - Gaithersburg MD

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Metal configurable register file Grant 9,811,628 - Park , et al. November 7, 2	2017-11-07
Metal configurable hybrid memory Grant 9,590,634 - Park , et al. March 7, 2	2017-03-07
Flexible, space-efficient I/O circuitry for integrated circuits Grant 9,577,640 - Park , et al. February 21, 2	2017-02-21
Flexible, space-efficient I/O circuitry for integrated circuits Grant 9,166,593 - Park , et al. October 20, 2	2015-10-20
Gate array architecture with multiple programmable regions App 20150048425 - Park; Jonathan C. ; et al.	2015-02-19
Gate array architecture with multiple programmable regions Grant 8,788,984 - Park , et al. July 22, 2	2014-07-22
Flexible, space-efficient I/O circuitry for integrated circuits Grant 8,773,163 - Park , et al. July 8, 2	2014-07-08
Gate array architecture with multiple programmable regions App 20130334576 - Park; Jonathan C ; et al.	2013-12-19
Gate array architecture with multiple programmable regions Grant 8,533,641 - Park , et al. September 10, 2	2013-09-10
Gate Array Architecture With Multiple Programmable Regions App 20130087834 - Park; Jonathan C. ; et al.	2013-04-11
High density gate array cell architecture with metallization routing tracks having a variable pitch Grant 5,990,502 - Park November 23, 1	1999-11-23

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