Park; Jae Eon

Patent Applications and Registrations

Patent applications and USPTO patent grants for Park; Jae Eon.The latest application filed is for "silicon precursor compounds and method for forming silicon-containing films".

Company Profile

2.7.13

Park; Jae Eon - GyeongGi-Do KR
PARK; Jae Eon - HwaSung-City KR
PARK; Jae Eon - HwaSung KR
Park; Jae-eon - Fishkill NY
Park; Jae-eon - Yongsin-si KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for forming carbon rich silicon-containing films Grant 11,414,750 - Cho , et al. August 16, 2	2022-08-16
Silicon Precursor Compounds And Method For Forming Silicon-containing Films App 20210395884 - CHO; Sungsil ; et al.	2021-12-23
Precursors And Methods For Preparing Silicon-containing Films App 20210301400 - LEE; SangJin ; et al.	2021-09-30
Haloalkynyl Dicobalt Hexacarbonyl Precursors For Chemical Vapor Deposition Of Cobalt App 20210082708 - HAN; Sangbum ; et al.	2021-03-18
Method For Forming Carbon Rich Silicon-containing Films App 20200354830 - CHO; Sungsil ; et al.	2020-11-12
Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein Grant 7,838,390 - Kim , et al. November 23, 2	2010-11-23
CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein Grant 7,800,134 - Lee , et al. September 21, 2	2010-09-21
Methods of Forming Electrical Interconnects Using Thin Electrically Insulating Liners in Contact Holes App 20100029072 - Park; Jae-Eon ; et al.	2010-02-04
CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein App 20090194817 - Lee; Kyoung-woo ; et al.	2009-08-06
Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques Grant 7,541,288 - Kim , et al. June 2, 2	2009-06-02
Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby Grant 7,534,678 - Lee , et al. May 19, 2	2009-05-19
Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein App 20090098706 - Kim; Jun-jung ; et al.	2009-04-16
Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby App 20080242015 - Lee; Kyoung-woo ; et al.	2008-10-02
Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques App 20080220584 - Kim; Jun-jung ; et al.	2008-09-11
Methods of Forming CMOS Integrated Circuits Using Gate Sidewall Spacer Reduction Techniques App 20080124859 - Sun; Min Chul ; et al.	2008-05-29
Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner App 20080029823 - Park; Jae-Eon ; et al.	2008-02-07
Method of fabricating semiconductor device Grant 7,323,419 - Jung , et al. January 29, 2	2008-01-29
Methods of fabricating semiconductor devices having a dual stress liner Grant 7,297,584 - Park , et al. November 20, 2	2007-11-20
Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner App 20070082439 - Park; Jae-Eon ; et al.	2007-04-12
Method of fabricating semiconductor device App 20060175289 - Jung; Hyung-suk ; et al.	2006-08-10

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