Park; Hyoun-Soo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Park; Hyoun-Soo.The latest application filed is for "integrated circuit for quadruple patterning lithography, and computing system and computer-implemented method for designing integrated circuit".

Company Profile

2.6.6

Park; Hyoun-Soo - Seoul KR
Park; Hyoun Soo - Daegu KR
Park; Hyoun Soo - Daegu-city KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computing system for performing colorless routing for quadruple patterning lithography Grant 10,621,300 - Won , et al.	2020-04-14
Integrated circuit, and computing system and computer-implemented method for designing integrated circuit Grant 10,430,546 - Won , et al. O	2019-10-01
Integrated Circuit, And Computing System And Computer-implemented Method For Designing Integrated Circuit App 20180173838 - Won; Hyo-Sig ; et al.	2018-06-21
Integrated Circuit For Quadruple Patterning Lithography, And Computing System And Computer-implemented Method For Designing Integrated Circuit App 20180173837 - WON; HYO-SIG ; et al.	2018-06-21
Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same Grant 9,524,922 - Lim , et al. December 20, 2	2016-12-20
Integrated Circuit Having Main Route And Detour Route For Signal Transmission And Integrated Circuit Package Including The Same App 20150371926 - LIM; Kyounghwan ; et al.	2015-12-24
Semiconductor integrated circuit and an operating method thereof, a timing verifying method for a semiconductor integrated circuit and a test method of a semiconductor integrated circuit Grant 8,928,394 - Park January 6, 2	2015-01-06
Semiconductor Integrated Circuit And An Operating Method Thereof, A Timing Verifying Method For A Semiconductor Integrated Circuit And A Test Method Of A Semiconductor Integrated Circuit App 20140132334 - Park; Hyoun Soo	2014-05-15
Method of timing criticality calculation for statistical timing optimization of VLSI circuit Grant 8,046,724 - Park , et al. October 25, 2	2011-10-25
Single supply pass gate level converter for multiple supply voltage system Grant 7,961,028 - An , et al. June 14, 2	2011-06-14
Method Of Timing Criticality Calculation For Statistical Timing Optimization Of Vlsi Circuit App 20100242006 - Park; Hyoun Soo ; et al.	2010-09-23
Single Supply Pass Gate Level Converter For Multiple Supply Voltage System App 20100156371 - An; Jiyeon ; et al.	2010-06-24

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