Park; Byung-Iyul

Patent Applications and Registrations

Patent applications and USPTO patent grants for Park; Byung-Iyul.The latest application filed is for "wafer-to-wafer bonding structure".

Company Profile

0.10.12

Park; Byung-Iyul - Seoul KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fan out wafer level package type semiconductor package and package on package type semiconductor package including the same Grant 10,153,219 - Jeon , et al. Dec	2018-12-11
Integrated circuit devices having through-silicon vias and methods of manufacturing such devices Grant 9,735,090 - Choi , et al. August 15, 2	2017-08-15
Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages Grant 9,698,051 - Chun , et al. July 4, 2	2017-07-04
Semiconductor device and method of fabricating the same Grant 9,530,726 - Moon , et al. December 27, 2	2016-12-27
Wafer-to-wafer Bonding Structure App 20160013160 - CHUN; Jin-ho ; et al.	2016-01-14
Integrated circuit devices including a through-silicon via structure and methods of fabricating the same Grant 9,214,411 - Park , et al. December 15, 2	2015-12-15
Semiconductor Chips Having Through Silicon Vias And Related Fabrication Methods And Semiconductor Packages App 20150111346 - Chun; Jin-ho ; et al.	2015-04-23
Integrated Circuit Devices Including a Through-Silicon Via Structure and Methods of Fabricating the Same App 20150102497 - Park; Jae-Hwa ; et al.	2015-04-16
Wafer Processing Methods App 20140106649 - KIM; Tae-yeong ; et al.	2014-04-17
Integrated Circuit Devices Including A Via Structure And Methods Of Fabricating Integrated Circuit Devices Including A Via Structure App 20140070426 - Park; Jae-hwa ; et al.	2014-03-13
Semiconductor Devices Including Dummy Solder Bumps App 20130221519 - Hwang; Son-kwan ; et al.	2013-08-29
Integrated Circuit Device Including Through-silicon Via Structure Having Offset Interface App 20130119547 - Kim; Su-kyoung ; et al.	2013-05-16
Method of forming through silicon via of semiconductor device using low-k dielectric material Grant 8,426,308 - Han , et al. April 23, 2	2013-04-23
Conductive Layer Buried-type Substrate, Method Of Forming The Conductive Layer Buried-type Substrate, And Method Of Fabricating Semiconductor Device Using The Conductive Layer Buried-type Substrate App 20120052635 - Kang; Pil-kyu ; et al.	2012-03-01
Semiconductor Device Including Fuse App 20100193902 - SHIN; Seung-woo ; et al.	2010-08-05

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