| Patent | Date |
|---|
Methods And Apparatus For Forming Dual Metal Interconnects
App 20210320064 - PARIKH; SUKETU A. ; et al. | 2021-10-14 |
Methods and apparatus for forming dual metal interconnects
Grant 11,075,165 - Parikh , et al. July 27, 2 | 2021-07-27 |
Methods and apparatus for fabrication of self aligning interconnect structure
Grant 11,049,770 - Parikh June 29, 2 | 2021-06-29 |
Methods And Apparatus For Forming Dual Metal Interconnects
App 20210020569 - PARIKH; SUKETU A. ; et al. | 2021-01-21 |
Systems and methods for improved performance in semiconductor processing
Grant 10,892,198 - Rodrigo , et al. January 12, 2 | 2021-01-12 |
Simultaneous metal patterning for 3D interconnects
Grant 10,867,858 - Parikh December 15, 2 | 2020-12-15 |
Methods And Apparatus For Fabrication Of Self-aligning Interconnect Structure
App 20200303254 - PARIKH; SUKETU A. | 2020-09-24 |
Simultaneous Metal Patterning For 3d Interconnects
App 20200091002 - Parikh; Suketu A. | 2020-03-19 |
Systems And Methods For Improved Performance In Semiconductor Processing
App 20200091018 - Rodrigo; Chirantha P. ; et al. | 2020-03-19 |
Methods for forming an interconnect pattern on a substrate
Grant 9,437,479 - Parikh , et al. September 6, 2 | 2016-09-06 |
Methods For Forming An Interconnect Pattern On A Substrate
App 20150140805 - PARIKH; Suketu A. ; et al. | 2015-05-21 |
Copper wiring module control
Grant 8,005,634 - Shanmugasundram , et al. August 23, 2 | 2011-08-23 |
Etch depth control for dual damascene fabrication process
Grant 7,572,734 - Naik , et al. August 11, 2 | 2009-08-11 |
Integrated Circuit Interconnect Lines Having Reduced Line Resistance
App 20080108215 - Parikh; Suketu A. | 2008-05-08 |
Integrated Circuit Interconnect Lines Having Reduced Line Resistance
App 20080105968 - Parikh; Suketu A. | 2008-05-08 |
Etch Depth Control For Dual Damascene Fabrication Process
App 20080102638 - NAIK; MEHUL ; et al. | 2008-05-01 |
Copper Wiring Module Control
App 20070122921 - Shanmugasundram; Arulkumar ; et al. | 2007-05-31 |
Selective metal encapsulation schemes
Grant 7,205,228 - Padhi , et al. April 17, 2 | 2007-04-17 |
Techniques for triple and quadruple damascene fabrication
Grant 6,940,170 - Parikh September 6, 2 | 2005-09-06 |
Selective metal encapsulation schemes
App 20040248409 - Padhi, Deenesh ; et al. | 2004-12-09 |
Method for forming silicon containing layers on a substrate
Grant 6,656,840 - Rajagopalan , et al. December 2, 2 | 2003-12-02 |
Method For Forming Silicon Containing Layers On A Substrate
App 20030203614 - Rajagopalan, Nagarajan ; et al. | 2003-10-30 |
Copper wiring module control
App 20030199112 - Shanmugasundram, Arulkumar ; et al. | 2003-10-23 |
Copper interconnect with sidewall copper-copper contact between metal and via
App 20030194872 - Parikh, Suketu A. ; et al. | 2003-10-16 |
Selective metal passivated copper interconnect with zero etch stops
App 20030148618 - Parikh, Suketu A. | 2003-08-07 |
Misalignment tolerant techniques for dual damascene fabrication
Grant 6,594,540 - Parikh July 15, 2 | 2003-07-15 |
Dual Damascene Misalignment Tolerant Techniques For Vias And Sacrificial Etch Segments
App 20030089987 - PARIKH, SUKETU A. | 2003-05-15 |
Integrated equipment set for forming an interconnect on a substrate
App 20030074098 - Cheung, Robin W. ; et al. | 2003-04-17 |
Integrated circuit interconnect lines having sidewall layers
Grant 6,391,771 - Naik , et al. May 21, 2 | 2002-05-21 |
Techniques for triple and quadruple damascene fabrication
App 20010041436 - Parikh, Suketu A. | 2001-11-15 |
Techniques for triple and quadruple damascene fabrication
App 20010036719 - Parikh, Suketu A. | 2001-11-01 |
Techniques for triple and quadruple damascene fabrication
Grant 6,225,207 - Parikh May 1, 2 | 2001-05-01 |
Misalignment tolerant techniques for dual damascene fabrication
Grant 6,127,263 - Parikh October 3, 2 | 2000-10-03 |
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