| Patent | Date |
|---|
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20210364569 - Narayanan; Prakash ; et al. | 2021-11-25 |
Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry
Grant 11,119,152 - Narayanan , et al. September 14, 2 | 2021-09-14 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20200174069 - Narayanan; Prakash ; et al. | 2020-06-04 |
Compressed scan chains with three input mask gates and registers
Grant 10,591,540 - Narayanan , et al. | 2020-03-17 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20180210030 - Narayanan; Prakash ; et al. | 2018-07-26 |
Compressed scan chains with three input mask gates and registers
Grant 9,952,283 - Narayanan , et al. April 24, 2 | 2018-04-24 |
Test circuit providing different levels of concurrency among radio cores
Grant 9,581,645 - Sontakke , et al. February 28, 2 | 2017-02-28 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20160069958 - Narayanan; Prakash ; et al. | 2016-03-10 |
Decompressed scan chain masking circuit shift register with log2(n/n) cells
Grant 9,229,055 - Narayanan , et al. January 5, 2 | 2016-01-05 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20150285860 - Narayanan; Prakash ; et al. | 2015-10-08 |
Scan chain masking qualification circuit shift register and bit-field decoders
Grant 9,091,729 - Narayanan , et al. July 28, 2 | 2015-07-28 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20150006987 - Narayanan; Prakash ; et al. | 2015-01-01 |
Masking circuit removing unknown bit from cell in scan chain
Grant 8,887,018 - Narayanan , et al. November 11, 2 | 2014-11-11 |
Built-in Self-test Methods, Circuits And Apparatus For Concurrent Test Of Rf Modules With A Dynamically Configurable Test Structure
App 20140232422 - Sontakke; Adesh ; et al. | 2014-08-21 |
Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structure
Grant 8,694,276 - Sontakke , et al. April 8, 2 | 2014-04-08 |
Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
Grant 8,671,329 - Kumar , et al. March 11, 2 | 2014-03-11 |
Low Overhead And Timing Improved Architecture For Performing Error Checking And Correction For Memories And Buses In System-on-chips, And Other Circuits, Systems And Processes
App 20130246889 - Kumar; Sanjay ; et al. | 2013-09-19 |
Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processes
Grant 8,438,344 - Kumar , et al. May 7, 2 | 2013-05-07 |
Built-in Self-test Methods, Circuits And Apparatus For Concurrent Test Of Rf Modules With A Dynamically Configurable Test Structure
App 20120191400 - Sontakke; Adesh Sharadrao ; et al. | 2012-07-26 |
Compressed Scan Chain Diagnosis By Internal Chain Observation, Processes, Circuits, Devices And Systems
App 20110307750 - Narayanan; Prakash ; et al. | 2011-12-15 |
Low Overhead And Timing Improved Architecture For Performing Error Checking And Correction For Memories And Buses In System-on-chips, And Other Circuits, Systems And Processes
App 20110225475 - Kumar; Sanjay ; et al. | 2011-09-15 |
Generating scan test vectors for proprietary cores using pseudo pins
App 20070288797 - Chakravarthy; Srinivasa ; et al. | 2007-12-13 |
Generating an abbreviated netlist including pseudopin inputs and output nodes
Grant 7,203,880 - Chakravarthy , et al. April 10, 2 | 2007-04-10 |
At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
Grant 7,134,061 - Agashe , et al. November 7, 2 | 2006-11-07 |
Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components
Grant 6,925,408 - Premy , et al. August 2, 2 | 2005-08-02 |
Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital components
App 20050065747 - Premy, Amit ; et al. | 2005-03-24 |
At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platform
App 20050055615 - Agashe, Anupama Anlruddha ; et al. | 2005-03-10 |
Using pseudo-pins in generating scan test vectors for testing an embedded core while maintaining the IP contained therein
App 20040158789 - Chakravarthy, Srinivasa ; et al. | 2004-08-12 |
Generating netlist test vectors by stripping references to a pseudo input
Grant 6,697,982 - Chakravarthy , et al. February 24, 2 | 2004-02-24 |
Using pseudo-pins in generating scan test vectors for testing an embedded core while maintaining the IP contained therein
App 20030014703 - Chakravarthy, Srinivasa ; et al. | 2003-01-16 |
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