loadpatents
name:-0.0082521438598633
name:-0.01032280921936
name:-0.012593030929565
Parekh; Sinjeet Dhanvantray Patent Filings

Parekh; Sinjeet Dhanvantray

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parekh; Sinjeet Dhanvantray.The latest application filed is for "phase cancellation in a phase-locked loop".

Company Profile
12.8.10
  • Parekh; Sinjeet Dhanvantray - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Cycle slip detection and correction in phase-locked loop
Grant 10,868,550 - Janardhanan , et al. December 15, 2
2020-12-15
Phase Cancellation In A Phase-locked Loop
App 20200321969 - JANARDHANAN; Jayawardan ;   et al.
2020-10-08
Phase cancellation in a phase-locked loop
Grant 10,727,846 - Janardhanan , et al.
2020-07-28
Time-to-digital converter circuit
Grant 10,691,074 - Yao , et al.
2020-06-23
Cycle slip detection and correction in phase-locked loop
Grant 10,686,456 - Janardhanan , et al.
2020-06-16
Cycle Slip Detection And Correction In Phase-locked Loop
App 20200177192 - JANARDHANAN; Jayawardan ;   et al.
2020-06-04
Phase Cancellation In A Phase-locked Loop
App 20200021301 - JANARDHANAN; Jayawardan ;   et al.
2020-01-16
Crystal oscillator offset trim in a phase-locked loop
Grant 10,505,555 - Parekh , et al. Dec
2019-12-10
Phase cancellation in a phase-locked loop
Grant 10,498,344 - Janardhanan , et al. De
2019-12-03
Time-to-digital converter circuit
Grant 10,496,041 - Yao , et al. De
2019-12-03
Switch between input reference clocks of different frequencies in a phase locked loop (PLL) without phase impact
Grant 10,491,222 - Parekh , et al. Nov
2019-11-26
Time-to-digital Converter Circuit
App 20190339650 - YAO; Henry ;   et al.
2019-11-07
Time-to-digital Converter Circuit
App 20190339651 - YAO; Henry ;   et al.
2019-11-07
Three Loop Phase-locked Loop
App 20190288695 - YAO; Henry ;   et al.
2019-09-19
Crystal Oscillator Offset Trim In A Phase-locked Loop
App 20190288699 - PAREKH; Sinjeet Dhanvantray ;   et al.
2019-09-19
Switch Between Input Reference Clocks Of Different Frequencies In A Phase Locked Loop (pll) Without Phase Impact
App 20190288694 - PAREKH; Sinjeet Dhanvantray ;   et al.
2019-09-19
Cycle Slip Detection And Correction In Phase-locked Loop
App 20190280700 - JANARDHANAN; Jayawardan ;   et al.
2019-09-12
Phase Cancellation In A Phase-locked Loop
App 20190280699 - JANARDHANAN; Jayawardan ;   et al.
2019-09-12

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