Parat; Krishna

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parat; Krishna.The latest application filed is for "weak erase pulse".

Company Profile

8.39.44

Parat; Krishna - Palo Alto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Weak Erase Pulse App 20220293189 - Zhang; Chao ; et al.	2022-09-15
Method And Apparatus To Mitigate Hot Electron Read Disturbs In 3d Nand Devices App 20220284968 - Cao; Wei ; et al.	2022-09-08
Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices Grant 11,355,199 - Cao , et al. June 7, 2	2022-06-07
Flash memory components and methods Grant 11,322,508 - Parat , et al. May 3, 2	2022-05-03
Method And Apparatus To Mitigate Hot Electron Read Disturbs In 3d Nand Devices App 20220028459 - Cao; Wei ; et al.	2022-01-27
Apparatuses, Systems, And Methods For Heating A Memory Device App 20210240388 - Hazeghi; Arash ; et al.	2021-08-05
Sense flags in a memory device Grant 11,029,861 - Ahmed , et al. June 8, 2	2021-06-08
Memory arrays with bonded and shared logic circuitry Grant 10,923,450 - Fastow , et al. February 16, 2	2021-02-16
Memory Arrays With Bonded And Shared Logic Circuitry App 20200395328 - Fastow; Richard ; et al.	2020-12-17
Memory device with reduced capacitance Grant 10,861,867 - Hasnat , et al. December 8, 2	2020-12-08
Channel conductivity in memory structures Grant 10,854,746 - Majhi , et al. December 1, 2	2020-12-01
Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming Grant 10,847,233 - Goda , et al. November 24, 2	2020-11-24
3-dimensional flash memory with increased floating gate length Grant 10,784,274 - Agarwal , et al. Sept	2020-09-22
Channel Conductivity In Memory Structures App 20200152793 - Majhi; Prashant ; et al.	2020-05-14
Modified floating gate and dielectric layer geometry in 3D memory arrays Grant 10,622,450 - Koval , et al.	2020-04-14
Sense Flags In A Memory Device App 20190369887 - Ahmed; Shafqat ; et al.	2019-12-05
Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming Grant 10,438,672 - Goda , et al. O	2019-10-08
Memory Devices And Apparatus Configured To Apply Positive Voltage Levels To Data Lines For Memory Cells Selected For And Inhibit App 20190295668 - Goda; Akira ; et al.	2019-09-26
Sense flags in a memory device Grant 10,409,506 - Ahmed , et al. Sept	2019-09-10
Modified Floating Gate And Dielectric Layer Geometry In 3d Memory Arrays App 20190043960 - Koval; Randy ; et al.	2019-02-07
Flash Memory Components And Methods App 20190043875 - PARAT; KRISHNA ; et al.	2019-02-07
Memory Device With Reduced Capacitance App 20190043882 - Hasnat; Khaled ; et al.	2019-02-07
Sense Flags In A Memory Device App 20180373451 - Ahmed; Shafqat ; et al.	2018-12-27
Sense operation flags in a memory device Grant 10,126,967 - Ahmed , et al. November 13, 2	2018-11-13
Memory Devices And Apparatus Configured To Apply Positive Voltage Levels To Data Lines For Memory Cells Selected For And Inhibited From Programming App 20180322933 - Goda; Akira ; et al.	2018-11-08
Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source Grant 10,049,756 - Goda , et al. August 14, 2	2018-08-14
Memory Devices That Apply A Programming Potential To A Memory Cell In A String Coupled To A Source And Data Line Concurrently With Biasing The Data Line To A Greater Potential Than The Source App 20170206977 - Goda; Akira ; et al.	2017-07-20
Operating memory devices to apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source Grant 9,646,702 - Goda , et al. May 9, 2	2017-05-09
Sense Operation Flags In A Memory Device App 20170075613 - Ahmed; Shafqat ; et al.	2017-03-16
Sense operation flags in a memory device Grant 9,519,582 - Ahmed , et al. December 13, 2	2016-12-13
Memory devices and programming memory arrays thereof Grant 9,437,304 - Goda , et al. September 6, 2	2016-09-06
Memory Devices And Biasing Methods For Memory Devices App 20160133327 - Goda; Akira ; et al.	2016-05-12
Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string Grant 9,251,907 - Goda , et al. February 2, 2	2016-02-02
Memory Devices And Programming Memory Arrays Thereof App 20160005474 - Goda; Akira ; et al.	2016-01-07
Sense Operation Flags In A Memory Device App 20150363313 - Ahmed; Shafqat ; et al.	2015-12-17
Memory devices and programming memory arrays thereof Grant 9,171,626 - Goda , et al. October 27, 2	2015-10-27
Sense operation flags in a memory device Grant 9,135,998 - Ahmed , et al. September 15, 2	2015-09-15
Memory Devices And Programming Memory Arrays Thereof App 20140029345 - Goda; Akira ; et al.	2014-01-30
Memory Devices And Biasing Methods For Memory Devices App 20130258781 - Goda; Akira ; et al.	2013-10-03
Independent well bias management in a memory device Grant 8,498,159 - Goda , et al. July 30, 2	2013-07-30
Memory Device Having Improved Programming Operation App 20130016569 - Damle; Prashant S. ; et al.	2013-01-17
Memory device having improved programming operation Grant 8,331,160 - Damle , et al. December 11, 2	2012-12-11
Independent Well Bias Management In A Memory Device App 20120218824 - Goda; Akira ; et al.	2012-08-30
Sense Operation Flags In A Memory Device App 20120117306 - Ahmed; Shafqat ; et al.	2012-05-10
Independent well bias management in a memory device Grant 8,174,893 - Goda , et al. May 8, 2	2012-05-08
Apparatus and methods for improved flash cell characteristics Grant 8,072,022 - Kalavade , et al. December 6, 2	2011-12-06
Memory Device Having Improved Programming Operation App 20110280085 - Damle; Prashant S. ; et al.	2011-11-17
Memory device having improved programming operation Grant 7,990,772 - Damle , et al. August 2, 2	2011-08-02
Floating gate structures Grant 7,989,289 - Krishnamohan , et al. August 2, 2	2011-08-02
Independent Well Bias Management In A Memory Device App 20110090739 - Goda; Akira ; et al.	2011-04-21
Isolated P-well architecture for a memory device Grant 7,920,419 - Damle , et al. April 5, 2	2011-04-05
Boosting seed voltage for a memory device Grant 7,835,187 - Tamada , et al. November 16, 2	2010-11-16
Memory Device Having Improved Programming Operation App 20100232234 - Damle; Prashant S. ; et al.	2010-09-16
Isolated P-well Architecture for a Memory Device App 20100195383 - Damle; Prashant ; et al.	2010-08-05
Apparatus and methods for improved flash cell characteristics App 20100155807 - Kalavade; Pranav ; et al.	2010-06-24
Boosting Seed Voltage For A Memory Device App 20100110795 - Tamada; Satoru ; et al.	2010-05-06
Floating Gate Structures App 20090283817 - Krishnamohan; Tejas ; et al.	2009-11-19
Managing floating gate-to-floating gate spacing to support scalability Grant 7,582,530 - Chao , et al. September 1, 2	2009-09-01
Non-volatile Memory Cell With Multi-layer Blocking Dielectric App 20090001443 - Krishnamohan; Tejas ; et al.	2009-01-01
Enabling flash cell scaling by shaping of the floating gate using spacers App 20080237680 - Pangal; Kiran ; et al.	2008-10-02
Managing floating gate-to-floating gate spacing to support scalability App 20080001208 - Chao; Henry ; et al.	2008-01-03
Method of forming non-volatile memory cell using spacers and non-volatile memory cell formed according to the method App 20070114592 - Soss; Steven R. ; et al.	2007-05-24
Memory device and method for erasing memory Grant 7,187,591 - Fastow , et al. March 6, 2	2007-03-06
Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method Grant 7,183,162 - Soss , et al. February 27, 2	2007-02-27
Memory Device And Method For Erasing Memory App 20070002620 - Fastow; Richard ; et al.	2007-01-04
Dual trench isolation using single critical lithographic patterning Grant 6,949,801 - Parat , et al. September 27, 2	2005-09-27
Integrated memory cell and method of fabrication Grant 6,943,071 - Fazio , et al. September 13, 2	2005-09-13
Dual trench isolation using single critical lithographic patterning Grant 6,849,518 - Parat , et al. February 1, 2	2005-02-01
Dual trench isolation using single critical lithographic patterning App 20040058508 - Parat, Krishna ; et al.	2004-03-25
Dual trench isolation using single critical lithographic patterning App 20030211702 - Parat, Krishna ; et al.	2003-11-13
Integrated memory cell and method of fabrication Grant 6,518,618 - Fazio , et al. February 11, 2	2003-02-11
Integrated memory cell and method of fabrication App 20020149050 - Fazio, Albert ; et al.	2002-10-17
Novel flash integrated circuit and its method of fabrication App 20010024857 - Parat, Krishna ; et al.	2001-09-27
Method and apparatus for providing electrostatic discharge protection for high voltage inputs Grant 5,825,603 - Parat , et al. October 20, 1	1998-10-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.