Parameswaran; Suresh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Parameswaran; Suresh.The latest application filed is for "circuits and methods for programming integrated circuit input and output impedances".

Company Profile

0.7.1

Parameswaran; Suresh - Fremont CA
Parameswaran; Suresh - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Test vehicle for package testing Grant 11,073,550 - Gong , et al. July 27, 2	2021-07-27
Circuits and methods for programming integrated circuit input and output impedances Grant 8,040,164 - Parameswaran , et al. October 18, 2	2011-10-18
Circuit and method for cascading programmable impedance matching in a multi-chip system Grant 7,728,619 - Tzou , et al. June 1, 2	2010-06-01
Memory having read disturb test mode Grant 7,719,908 - Tzou , et al. May 18, 2	2010-05-18
Configurable data path architecture and clocking scheme Grant 7,535,772 - Parameswaran , et al. May 19, 2	2009-05-19
Circuits and methods for programming integrated circuit input and output impedances App 20090085614 - Parameswaran; Suresh ; et al.	2009-04-02
Single late-write for standard synchronous SRAMs Grant 7,403,446 - Parameswaran , et al. July 22, 2	2008-07-22
Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses Grant 7,142,477 - Tran , et al. November 28, 2	2006-11-28

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