| Patent | Date |
|---|
Apparatuses And Methods For A Processor Architecture
App 20220237123 - Brandt; Jason W. ; et al. | 2022-07-28 |
Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor
Grant 6,349,380 - Shahidzadeh , et al. February 19, 2 | 2002-02-19 |
Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
Grant 6,079,014 - Papworth , et al. June 20, 2 | 2000-06-20 |
Method and apparatus for implementing a branch target buffer in CISC processor
Grant 5,903,751 - Hoyt , et al. May 11, 1 | 1999-05-11 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,842,036 - Hinton , et al. November 24, 1 | 1998-11-24 |
Register alias table update to indicate architecturally visible state
Grant 5,826,094 - Colwell , et al. October 20, 1 | 1998-10-20 |
Method and apparatus for performing multiple load operations to the same memory location in a computer system
Grant 5,826,109 - Abramson , et al. October 20, 1 | 1998-10-20 |
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit
Grant 5,812,839 - Hoyt , et al. September 22, 1 | 1998-09-22 |
Method and apparatus for changing flow of control in a processor
Grant 5,809,271 - Colwell , et al. September 15, 1 | 1998-09-15 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,809,325 - Hinton , et al. September 15, 1 | 1998-09-15 |
Method and apparatus for dynamic allocation of multiple buffers in a processor
Grant 5,778,245 - Papworth , et al. July 7, 1 | 1998-07-07 |
Out-of-order processor with a memory subsystem which handles speculatively dispatched load operations
Grant 5,751,983 - Abramson , et al. May 12, 1 | 1998-05-12 |
Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
Grant 5,721,855 - Hinton , et al. February 24, 1 | 1998-02-24 |
Method and apparatus for dispatching and executing a load operation to memory
Grant 5,717,882 - Abramson , et al. February 10, 1 | 1998-02-10 |
Method and apparatus for implementing a set-associative branch target buffer
Grant 5,706,492 - Hoyt , et al. January 6, 1 | 1998-01-06 |
Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
Grant 5,687,338 - Boggs , et al. November 11, 1 | 1997-11-11 |
Speculative and committed resource files in an out-of-order processor
Grant 5,627,985 - Fetterman , et al. May 6, 1 | 1997-05-06 |
Method and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer system
Grant 5,606,670 - Abramson , et al. February 25, 1 | 1997-02-25 |
Method and apparatus for performing error correction on data from an external memory
Grant 5,604,753 - Bauer , et al. February 18, 1 | 1997-02-18 |
Method and apparatus for resolving return from subroutine instructions in a computer processor
Grant 5,604,877 - Hoyt , et al. February 18, 1 | 1997-02-18 |
Methods and apparatus for fordwarding buffered store data on an out-of-order execution computer system
Grant 5,588,126 - Abramson , et al. December 24, 1 | 1996-12-24 |
Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor
Grant 5,586,278 - Papworth , et al. December 17, 1 | 1996-12-17 |
Entry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversed
Grant 5,584,038 - Papworth , et al. December 10, 1 | 1996-12-10 |
Entry allocation in a circular buffer
Grant 5,584,037 - Papworth , et al. December 10, 1 | 1996-12-10 |
Hybrid execution unit for complex microprocessor
Grant 5,574,942 - Colwell , et al. November 12, 1 | 1996-11-12 |
Method and apparatus for implementing a set-associative branch target buffer
Grant 5,574,871 - Hoyt , et al. November 12, 1 | 1996-11-12 |
Method and apparatus for implementing a non-blocking translation lookaside buffer
Grant 5,564,111 - Glew , et al. October 8, 1 | 1996-10-08 |
Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
Grant 5,564,056 - Fetterman , et al. October 8, 1 | 1996-10-08 |
Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
Grant 5,561,814 - Glew , et al. October 1, 1 | 1996-10-01 |
Circuit and method for scheduling instructions by predicting future availability of resources required for execution
Grant 5,555,432 - Hinton , et al. September 10, 1 | 1996-09-10 |
Apparatus for pipeline streamlining where resources are immediate or certainly retired
Grant 5,553,256 - Fetterman , et al. September 3, 1 | 1996-09-03 |
Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
Grant 5,546,597 - Martell , et al. August 13, 1 | 1996-08-13 |
Idiom recognizer within a register alias table
Grant 5,471,633 - Colwell , et al. November 28, 1 | 1995-11-28 |
Apparatus and method for handling string operations in a pipelined processor
Grant 5,404,473 - Papworth , et al. April 4, 1 | 1995-04-04 |
High bandwidth multiple computer bus apparatus
Grant 5,307,506 - Colwell , et al. April 26, 1 | 1994-04-26 |
Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus
Grant 5,179,680 - Colwell , et al. January 12, 1 | 1993-01-12 |
Instruction storage method with a compressed format using a mask word
Grant 5,057,837 - Colwell , et al. October 15, 1 | 1991-10-15 |
Hierarchical priority branch handling for parallel execution in a parallel processor
Grant 4,833,599 - Colwell , et al. May 23, 1 | 1989-05-23 |
Data processing apparatus and method employing instruction flow prediction
Grant 4,777,594 - Jones , et al. October 11, 1 | 1988-10-11 |
Data processing apparatus and method employing collision detection and prediction
Grant 4,760,519 - Papworth , et al. July 26, 1 | 1988-07-26 |
Memory access method and apparatus in multiple processor systems
Grant 4,561,051 - Rodman , et al. December 24, 1 | 1985-12-24 |
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