Paone; Phil Christopher Felice

Patent Applications and Registrations

Patent applications and USPTO patent grants for Paone; Phil Christopher Felice.The latest application filed is for "vertical stacking of field effect transistor structures for logic gates".

Company Profile

0.12.10

Paone; Phil Christopher Felice - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Vertical stacking of field effect transistor structures for logic gates Grant 8,754,417 - Christensen , et al. June 17, 2	2014-06-17
Vertical Stacking of Field Effect Transistor Structures for Logic Gates App 20130001701 - Christensen; Todd Alan ; et al.	2013-01-03
Vertical stacking of field effect transistor structures for logic gates Grant 8,314,001 - Christensen , et al. November 20, 2	2012-11-20
Method for creating 3-D single gate inverter Grant 8,114,747 - Paone , et al. February 14, 2	2012-02-14
Vertical Stacking of Field Effect Transistor Structures for Logic Gates App 20110248349 - Christensen; Todd Alan ; et al.	2011-10-13
Implementing eFuse resistance determination before initiating eFuse blow Grant 7,915,949 - Erickson , et al. March 29, 2	2011-03-29
3-D Single Gate Inverter App 20110059583 - Paone; Phil Christopher Felice ; et al.	2011-03-10
3-D single gate inverter Grant 7,868,391 - Paone , et al. January 11, 2	2011-01-11
3-d Single Gate Inverter App 20100308413 - Paone; Phil Christopher Felice ; et al.	2010-12-09
Implementing eFuse Resistance Determination Before Initiating eFuse Blow App 20100232248 - Erickson; Karl Robert ; et al.	2010-09-16
Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor Grant 7,764,531 - Aipperspach , et al. July 27, 2	2010-07-27
Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse Grant 7,733,722 - Aipperspach , et al. June 8, 2	2010-06-08
Method and circuit for implementing enhanced eFuse sense circuit Grant 7,729,188 - Aipperspach , et al. June 1, 2	2010-06-01
Method and circuit for implementing eFuse sense amplifier verification Grant 7,725,844 - Aipperspach , et al. May 25, 2	2010-05-25
Implementing Efuse sense amplifier testing without blowing the Efuse Grant 7,689,950 - Aipperspach , et al. March 30, 2	2010-03-30
Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor App 20100067319 - Aipperspach; Anthony Gus ; et al.	2010-03-18
Method and Circuit for Implementing Efuse Resistance Screening App 20090212850 - Aipperspach; Anthony Gus ; et al.	2009-08-27
Apparatus For Implementing Efuse Sense Amplifier Testing Without Blowing The Efuse App 20090175106 - Aipperspach; Anthony Gus ; et al.	2009-07-09
Method for implementing eFuse sense amplifier testing without blowing the eFuse Grant 7,489,572 - Aipperspach , et al. February 10, 2	2009-02-10
Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse App 20080169843 - Aipperspach; Anthony Gus ; et al.	2008-07-17
Method and Apparatus for Implementing Efuse Sense Amplifier Testing Without Blowing the Efuse App 20080170449 - Aipperspach; Anthony Gus ; et al.	2008-07-17

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