Panitz; Philipp

Patent Applications and Registrations

Patent applications and USPTO patent grants for Panitz; Philipp.The latest application filed is for "instruction scheduling approach to improve processor performance".

Company Profile

0.23.14

Panitz; Philipp - Boeblingen DE
Panitz; Philipp - Schoenaich DE
Panitz; Philipp - Laatzen DE
Panitz; Philipp - Garbsen N/A DE
Panitz; Philipp - Lehrte DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instruction scheduling approach to improve processor performance Grant 9,256,430 - Koehl , et al. February 9, 2	2016-02-09
Mechanism to speed-up multithreaded execution by register file write port reallocation Grant 9,207,995 - Boersma , et al. December 8, 2	2015-12-08
Apparatus and method for calculating an SHA-2 hash function in a general purpose processor Grant 9,164,725 - Boersma , et al. October 20, 2	2015-10-20
Techniques for reusing components of a logical operations functional block as an error correction code correction unit Grant 9,043,673 - Kaltenback , et al. May 26, 2	2015-05-26
Instruction Scheduling Approach To Improve Processor Performance App 20150127926 - KOEHL; Juergen ; et al.	2015-05-07
Instruction scheduling approach to improve processor performance Grant 8,972,961 - Koehl , et al. March 3, 2	2015-03-03
Byte selection and steering logic for combined byte shift and byte permute vector unit Grant 8,959,276 - Kaltenbach , et al. February 17, 2	2015-02-17
Byte selection and steering logic for combined byte shift and byte permute vector unit Grant 8,959,275 - Kaltenbach , et al. February 17, 2	2015-02-17
Instruction scheduling approach to improve processor performance Grant 8,935,685 - Koehl , et al. January 13, 2	2015-01-13
Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product Grant 8,903,882 - Boersma , et al. December 2, 2	2014-12-02
Method and system for calculating timing delay in a repeater network in an electronic circuit Grant 8,731,858 - Buehler , et al. May 20, 2	2014-05-20
Byte Selection And Steering Logic For Combined Byte Shift And Byte Permute Vector Unit App 20140129809 - Kaltenbach; Markus ; et al.	2014-05-08
Byte Selection And Steering Logic For Combined Byte Shift And Byte Permute Vector Unit App 20140101358 - Kaltenbach; Markus ; et al.	2014-04-10
Gate configuration determination and selection from standard cell library Grant 8,627,263 - Buechner , et al. January 7, 2	2014-01-07
Estimating power consumption of an electronic circuit Grant 8,612,911 - Buechner , et al. December 17, 2	2013-12-17
Techniques for Reusing Components of a Logical Operations Functional Block as an Error Correction Code Correction Unit App 20130227375 - Kaltenback; Markus ; et al.	2013-08-29
Glitch power reduction Grant 8,407,654 - Buechner , et al. March 26, 2	2013-03-26
Glitch Power Reduction App 20120266120 - Buechner; Thomas ; et al.	2012-10-18
Gate Configuration Determination And Selection From Standard Cell Library App 20120216168 - Buechner; Thomas ; et al.	2012-08-23
Instruction Scheduling Approach To Improve Processor Performance App 20120216016 - Koehl; Juergen ; et al.	2012-08-23
Estimating Power Consumption Of An Electronic Circuit App 20120216160 - Buechner; Thomas ; et al.	2012-08-23
Method And Data Processing Unit For Calculating At Least One Multiply-sum Of Two Carry-less Multiplications Of Two Input Operands, Data Processing Program And Computer Program Product App 20120150933 - Boersma; Maarten J. ; et al.	2012-06-14
Apparatus And Method For Calculating An Sha-2 Hash Function In A General Purpose Processor App 20120128149 - Boersma; Maarten J. ; et al.	2012-05-24
Mechanism To Speed-up Multithreaded Execution By Register File Write Port Reallocation App 20120110271 - Boersma; Maarten J. ; et al.	2012-05-03
Instruction Scheduling Approach To Improve Processor Performance App 20110289297 - Koehl; Juergen ; et al.	2011-11-24
Routing of wires of an electronic circuit Grant 8,015,527 - Buehler , et al. September 6, 2	2011-09-06
Method and System for Calculating Timing Delay in a Repeater Network in an Electronic Circuit App 20100100347 - Buehler; Markus ; et al.	2010-04-22
Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated Circuit App 20080059933 - Barke; Erich ; et al.	2008-03-06

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