Pangrle; Suzette K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pangrle; Suzette K..The latest application filed is for "electrical connector between die pad and z-interconnect for stacked die assemblies".

Company Profile

0.59.27

Pangrle; Suzette K. - Cupertino CA
Pangrle; Suzette K - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrical connector between die pad and z-interconnect for stacked die assemblies Grant 9,508,689 - Co , et al. November 29, 2	2016-11-29
Damascene metal-insulator-metal (MIM) device with improved scaleability Grant 9,343,666 - Pangrle , et al. May 17, 2	2016-05-17
Electrical Connector Between Die Pad And Z-interconnect For Stacked Die Assemblies App 20160027761 - Co; Reynaldo ; et al.	2016-01-28
Electrical connector between die pad and z-interconnect for stacked die assemblies Grant 9,153,517 - Co , et al. October 6, 2	2015-10-06
Semiconductor Die Having Fine Pitch Electrical Interconnects App 20150056753 - Barrie; Keith Lake ; et al.	2015-02-26
Stacked die assembly having reduced stress electrical interconnects Grant 8,912,661 - McGrath , et al. December 16, 2	2014-12-16
Diode and resistive memory device structures Grant 8,803,120 - Rathor , et al. August 12, 2	2014-08-12
Metal-insulator-metal-insulator-metal (MIMIM) memory device Grant 8,717,803 - Rathor , et al. May 6, 2	2014-05-06
Damascene Metal-insulator-metal (mim) Device Improved Scaleability App 20120276706 - PANGRLE; Suzette K. ; et al.	2012-11-01
Semiconductor die having fine pitch electrical interconnects App 20120248607 - Barrie; Keith Lake ; et al.	2012-10-04
Damascene metal-insulator-metal (MIM) device with improved scaleability Grant 8,232,175 - Pangrle , et al. July 31, 2	2012-07-31
Electrical Connector Between Die Pad and Z-Interconnect for Stacked Die Assemblies App 20120119385 - Co; Reynaldo ; et al.	2012-05-17
Metal-insulator-metal-insulator-metal (mimim) Memory Device App 20120081947 - RATHOR; Manuj ; et al.	2012-04-05
Diode And Resistive Memory Device Structures App 20120025161 - RATHOR; Manuj ; et al.	2012-02-02
Metal-insulator-metal-insulator-metal (MIMIM) memory device Grant 8,093,680 - Rathor , et al. January 10, 2	2012-01-10
Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device Grant 8,093,698 - Rathor , et al. January 10, 2	2012-01-10
Damascene metal-insulator-metal (MIM) device Grant 8,089,113 - Pangrle , et al. January 3, 2	2012-01-03
Test structures for development of metal-insulator-metal (MIM) devices Grant 8,084,770 - Avanzino , et al. December 27, 2	2011-12-27
Stacked Die Assembly Having Reduced Stress Electrical Interconnects App 20110272825 - McGrath; Scott ; et al.	2011-11-10
Semiconductor device built on plastic substrate Grant 8,044,387 - Buynoski , et al. October 25, 2	2011-10-25
Diode and resistive memory device structures Grant 8,035,099 - Rathor , et al. October 11, 2	2011-10-11
Processing a copolymer to form a polymer memory cell Grant 8,012,673 - Pangrle , et al. September 6, 2	2011-09-06
Stacked organic memory devices and methods of operating and fabricating Grant 8,003,436 - Tripsas , et al. August 23, 2	2011-08-23
Method to prevent alloy formation when forming layered metal oxides by metal oxidation Grant 7,790,497 - Avanzino , et al. September 7, 2	2010-09-07
Ordered porosity to direct memory element formation Grant 7,776,682 - Nickel , et al. August 17, 2	2010-08-17
Semiconductor Die Interconnect Formed By Aerosol Application Of Electrically Conductive Material App 20100140811 - Leal; Jeffrey S. ; et al.	2010-06-10
System and method for processing an organic memory cell Grant 7,632,706 - Yudanov , et al. December 15, 2	2009-12-15
Diode and resistive memory device structures App 20090212283 - Rathor; Manuj ; et al.	2009-08-27
Process for making a resistive memory cell with separately patterned electrodes Grant 7,566,628 - Liao , et al. July 28, 2	2009-07-28
Method to prevent alloy formation when forming layered metal oxides by metal oxidation App 20090163018 - Avanzino; Steven ; et al.	2009-06-25
Stacked Organic Memory Devices And Methods Of Operating And Fabricating App 20090081824 - Tripsas; Nicholas H. ; et al.	2009-03-26
Test Stuctures for development of metal-insulator-metal (MIM) devices App 20090072234 - Avanzino; Steven ; et al.	2009-03-19
Test structures for development of metal-insulator-metal (MIM) devices Grant 7,468,525 - Avanzino , et al. December 23, 2	2008-12-23
Structure And Process For A Resistive Memory Cell With Separately Patterned Electrodes App 20080308781 - Liao; Dongxiang ; et al.	2008-12-18
Stacked organic memory devices and methods of operating and fabricating Grant 7,465,956 - Tripsas , et al. December 16, 2	2008-12-16
Method of fabricating metal-insulator-metal (MIM) device with stable data retention Grant 7,384,800 - Avanzino , et al. June 10, 2	2008-06-10
Method Of Fabricating Metal-insulator-metal (mim) Device With Stable Data Retention App 20080127480 - Avanzino; Steven ; et al.	2008-06-05
Test structures for development of metal-insulator-metal (MIM) devices App 20080128691 - Avanzino; Steven ; et al.	2008-06-05
Damascene metal-insulator-metal (MIM) device App 20080132068 - Pangrle; Suzette K. ; et al.	2008-06-05
Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device App 20080130195 - Rathor; Manuj ; et al.	2008-06-05
Damascene metal-insulator-metal (MIM) device with improved scaleability App 20080123401 - Pangrle; Suzette K. ; et al.	2008-05-29
Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures Grant 7,232,765 - Avanzino , et al. June 19, 2	2007-06-19
System and method for processing an organic memory cell App 20070090343 - Yudanov; Nicolay F. ; et al.	2007-04-26
Stackable memory device and organic transistor structure App 20070007510 - Sokolik; Igor ; et al.	2007-01-11
Memory device with improved data retention App 20070007585 - Sokolik; Igor ; et al.	2007-01-11
Stacked organic memory devices and methods of operating and fabricating Grant 6,979,837 - Tripsas , et al. December 27, 2	2005-12-27
Planar polymer memory device Grant 6,977,389 - Tripsas , et al. December 20, 2	2005-12-20
Semiconductor component and method of manufacture Grant 6,943,096 - Wang , et al. September 13, 2	2005-09-13
Method of forming a selective barrier layer using a sacrificial layer Grant 6,869,878 - Adem , et al. March 22, 2	2005-03-22
Stacked organic memory devices and methods of operating and fabricating Grant 6,870,183 - Tripsas , et al. March 22, 2	2005-03-22
Self assembly of conducting polymer for formation of polymer memory cell Grant 6,852,586 - Buynoski , et al. February 8, 2	2005-02-08
Protection of low-k ILD during damascene processing with thin liner Grant 6,836,017 - Ngo , et al. December 28, 2	2004-12-28
Planar polymer memory device App 20040238864 - Tripsas, Nicholas H. ; et al.	2004-12-02
Stacked organic memory devices and methods of operating and fabricating App 20040217347 - Tripsas, Nicholas H. ; et al.	2004-11-04
Method for determining pore characteristics in porous materials Grant 6,791,081 - Ulfig , et al. September 14, 2	2004-09-14
Polymer memory device formed in via opening Grant 6,787,458 - Tripsas , et al. September 7, 2	2004-09-07
Phosphine treatment of low dielectric constant materials in semiconductor device manufacturing Grant 6,784,095 - Pangrle , et al. August 31, 2	2004-08-31
Implantation for the formation of CuX layer in an organic memory device Grant 6,770,905 - Buynoski , et al. August 3, 2	2004-08-03
Protection of low-k ILD during damascene processing with thin liner App 20040147117 - Ngo, Minh Van ; et al.	2004-07-29
Use of sic for preventing copper contamination of low-k dielectric layers Grant 6,756,672 - You , et al. June 29, 2	2004-06-29
Method(s) facilitating formation of memory cell(s) and patterned conductive Grant 6,753,247 - Okoroanyanwu , et al. June 22, 2	2004-06-22
Method of forming copper sulfide for memory cell Grant 6,746,971 - Ngo , et al. June 8, 2	2004-06-08
Stacked organic memory devices and methods of operating and fabricating App 20040084670 - Tripsas, Nicholas H. ; et al.	2004-05-06
Protection low-k ILD during damascene processing with thin liner Grant 6,723,635 - Ngo , et al. April 20, 2	2004-04-20
Vapor treatment for repairing damage of low-k dielectric Grant 6,713,382 - Pangrle , et al. March 30, 2	2004-03-30
Coherent diffusion barriers for integrated circuit interconnects Grant 6,710,452 - Wang , et al. March 23, 2	2004-03-23
Dual damascene metal interconnect structure with dielectric studs Grant 6,660,619 - Pangrle , et al. December 9, 2	2003-12-09
Spin on polymers for organic memory devices Grant 6,656,763 - Oglesby , et al. December 2, 2	2003-12-02
Plasma etch process for nonhomogenous film Grant 6,599,839 - Gabriel , et al. July 29, 2	2003-07-29
Silane treatment of low dielectric constant materials in semiconductor device manufacturing Grant 6,566,283 - Pangrle , et al. May 20, 2	2003-05-20
Method of forming low resistance barrier on low k interconnect Grant 6,555,461 - Woo , et al. April 29, 2	2003-04-29
Semiconductor device with variable composition low-k inter-layer dielectric and method of making Grant 6,518,646 - Hopper , et al. February 11, 2	2003-02-11
Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer Grant 6,509,267 - Woo , et al. January 21, 2	2003-01-21
Method of manufacturing a semiconductor structure with treatment to sacrificial stop layer producing diffusion to an adjacent low-k dielectric layer lowering the constant Grant 6,475,929 - Gabriel , et al. November 5, 2	2002-11-05
Metal interconnection structure with dummy vias Grant 6,468,894 - Yang , et al. October 22, 2	2002-10-22
Insulating and capping structure with preservation of the low dielectric constant of the insulating layer Grant 6,326,692 - Pangrle , et al. December 4, 2	2001-12-04
Method And System For Modifying And Densifying A Porous Film App 20010038889 - PANGRLE, SUZETTE K. ; et al.	2001-11-08
Method for removing anti-reflective coating layer using plasma etch process before contact CMP Grant 6,291,296 - Hui , et al. September 18, 2	2001-09-18
Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines Grant 6,174,743 - Pangrle , et al. January 16, 2	2001-01-16
Method of reducing metal voidings in 0.25 .mu.m AL interconnect Grant 6,143,672 - Ngo , et al. November 7, 2	2000-11-07
Anti-reflective coating layer for semiconductor device Grant 5,986,344 - Subramanion , et al. November 16, 1	1999-11-16

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.