loadpatents
name:-0.020927906036377
name:-0.025140047073364
name:-0.00050091743469238
Pang; Liang-Teck Patent Filings

Pang; Liang-Teck

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pang; Liang-Teck.The latest application filed is for "stitchable global clock for 3d chips".

Company Profile
0.29.28
  • Pang; Liang-Teck - White Plains NY
  • Pang; Liang-Teck - Albany CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Stitchable global clock for 3D chips
Grant 9,800,232 - Franch , et al. October 24, 2
2017-10-24
Tunable sector buffer for wide bandwidth resonant global clock distribution
Grant 9,612,612 - Bucelot , et al. April 4, 2
2017-04-04
Stitchable Global Clock For 3d Chips
App 20160211833 - FRANCH; ROBERT L. ;   et al.
2016-07-21
Stitchable global clock for 3D chips
Grant 9,348,357 - Franch , et al. May 24, 2
2016-05-24
Distributed phase detection for clock synchronization in multi-layer 3D stacks
Grant 9,231,603 - Liu , et al. January 5, 2
2016-01-05
Stitchable Global Clock For 3d Chips
App 20150378388 - FRANCH; ROBERT L. ;   et al.
2015-12-31
Distributed Phase Detection For Clock Synchronization In Multi-layer 3d Stacks
App 20150280722 - Liu; Yong ;   et al.
2015-10-01
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution
App 20150234422 - Bucelot; Thomas J. ;   et al.
2015-08-20
Circuit Technique To Electrically Characterize Block Mask Shifts
App 20150179536 - Acar; Emrah ;   et al.
2015-06-25
Tunable sector buffer for wide bandwidth resonant global clock distribution
Grant 9,058,130 - Bucelot , et al. June 16, 2
2015-06-16
Wide bandwidth resonant global clock distribution
Grant 9,054,682 - Bucelot , et al. June 9, 2
2015-06-09
Circuit technique to electrically characterize block mask shifts
Grant 8,969,104 - Acar , et al. March 3, 2
2015-03-03
Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
Grant 8,928,350 - Pang , et al. January 6, 2
2015-01-06
Defect detection on characteristically capacitive circuit nodes
Grant 8,860,425 - Pang , et al. October 14, 2
2014-10-14
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution
App 20140223210 - Bucelot; Thomas J. ;   et al.
2014-08-07
Wide Bandwidth Resonant Global Clock Distribution
App 20140218087 - Bucelot; Thomas J. ;   et al.
2014-08-07
Changing Resonant Clock Modes
App 20140167832 - Bucelot; Thomas J. ;   et al.
2014-06-19
Changing resonant clock modes
Grant 8,736,342 - Bucelot , et al. May 27, 2
2014-05-27
Variable resistance switch for wide bandwidth resonant global clock distribution
Grant 8,704,576 - Bucelot , et al. April 22, 2
2014-04-22
Circuit Technique To Electrically Characterize Block Mask Shifts
App 20130320340 - Acar; Emrah ;   et al.
2013-12-05
AC supply noise reduction in a 3D stack with voltage sensing and clock shifting
Grant 8,587,357 - Kim , et al. November 19, 2
2013-11-19
3D chip stack skew reduction with resonant clock and inductive coupling
Grant 8,576,000 - Kim , et al. November 5, 2
2013-11-05
Defect Detection on Characteristically Capacitive Circuit Nodes
App 20130229189 - Pang; Liang-Teck ;   et al.
2013-09-05
Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network
Grant 8,525,569 - Bucelot , et al. September 3, 2
2013-09-03
Programming the behavior of individual chips or strata in a 3D stack of integrated circuits
Grant 8,519,735 - Pang , et al. August 27, 2
2013-08-27
3D chip stack skew reduction with resonant clock and inductive coupling
Grant 8,466,739 - Kim , et al. June 18, 2
2013-06-18
3d Chip Stack Skew Reduction With Resonant Clock And Inductive Coupling
App 20130049826 - KIM; JAE-JOON ;   et al.
2013-02-28
Ac Supply Noise Reduction In A 3d Stack With Voltage Sensing And Clock Shifting
App 20130049828 - KIM; JAE-JOON ;   et al.
2013-02-28
Programming The Behavior Of Individual Chips Or Strata In A 3d Stack Of Integrated Circuits
App 20130049795 - PANG; LIANG-TECK ;   et al.
2013-02-28
3d Chip Stack Skew Reduction With Resonant Clock And Inductive Coupling
App 20130049824 - KIM; JAE-JOON ;   et al.
2013-02-28
Programming The Behavior Of Individual Chips Or Strata In A 3d Stack Of Integrated Circuits
App 20130049796 - PANG; LIANG-TECK ;   et al.
2013-02-28
Synchronizing Global Clocks In 3d Stacks Of Integrated Circuits By Shorting The Clock Network
App 20130049827 - BUCELOT; THOMAS J. ;   et al.
2013-02-28
Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator
Grant 7,864,625 - Carpenter , et al. January 4, 2
2011-01-04
Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance
Grant 7,760,565 - Kuang , et al. July 20, 2
2010-07-20
Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator
App 20100085823 - Carpenter; Gary D. ;   et al.
2010-04-08
Storage array including a local clock buffer with programmable timing
Grant 7,668,037 - Carpenter , et al. February 23, 2
2010-02-23
Pulsed ring oscillator circuit for storage cell read timing evaluation
Grant 7,620,510 - Carpenter , et al. November 17, 2
2009-11-17
Storage Array Including a Local Clock Buffer with Programmable Timing
App 20090116312 - Carpenter; Gary D. ;   et al.
2009-05-07
Wordline-To-Bitline Output Timing Ring Oscillator Circuit for Evaluating Storage Array Performance
App 20090027065 - Kuang; Jente B. ;   et al.
2009-01-29
Pulsed Ring Oscillator Circuit For Storage Cell Read Timing Evaluation
App 20080225615 - Carpenter; Gary D. ;   et al.
2008-09-18
Pulsed ring oscillator circuit for storage cell read timing evaluation
Grant 7,409,305 - Carpenter , et al. August 5, 2
2008-08-05

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