Pancholy; Ashish

Patent Applications and Registrations

Patent applications and USPTO patent grants for Pancholy; Ashish.The latest application filed is for "eye-safe laser navigation sensor".

Company Profile

0.13.3

Pancholy; Ashish - Milpitas CA
Pancholy; Ashish - Santa Clara CA
Pancholy; Ashish - Milipitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Eye-safe laser navigation sensor Grant 7,809,035 - Sanders , et al. October 5, 2	2010-10-05
Eye-safe laser navigation sensor App 20070230525 - Sanders; Steven ; et al.	2007-10-04
MRAM data line configuration and method of operation Grant 6,862,215 - Pancholy , et al. March 1, 2	2005-03-01
Memory circuit with selective address path Grant 6,775,191 - Pancholy , et al. August 10, 2	2004-08-10
Magnetic memory cell and method for assigning tunable writing currents Grant 6,683,815 - Chen , et al. January 27, 2	2004-01-27
Multi-level programmable voltage control and output buffer with selectable operating voltage Grant 6,664,810 - Pancholy , et al. December 16, 2	2003-12-16
Localized MRAM data line and method of operation Grant 6,639,831 - Pancholy , et al. October 28, 2	2003-10-28
Random Access Memory Having A Read/write Address Bus And Process For Writing To And Reading From The Same App 20020054535 - Arcoleo, Mathew R. ; et al.	2002-05-09
Method and apparatus to prevent latch-up in CMOS devices Grant 6,359,316 - Voss , et al. March 19, 2	2002-03-19
Random access memory having independent read port and write port and process for writing to and reading from the same App 20010043506 - Arcoleo, Mathew R. ; et al.	2001-11-22
Scan path circuitry including a programmable delay circuit Grant 6,286,118 - Churchill , et al. September 4, 2	2001-09-04
Synchronous random access memory having a read/write address bus and process for writing to and reading from the same Grant 6,262,937 - Arcoleo , et al. July 17, 2	2001-07-17
Scan path circuitry for programming a variable clock pulse width Grant 6,115,836 - Churchill , et al. September 5, 2	2000-09-05
Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method Grant 6,069,839 - Pancholy , et al. May 30, 2	2000-05-30
Test mode features for synchronous pipelined memories Grant 6,006,347 - Churchill , et al. December 21, 1	1999-12-21
Scan path circuitry including an output register having a flow through mode Grant 5,953,285 - Churchill , et al. September 14, 1	1999-09-14

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